Integration of strained Ge into advanced CMOS technology

Details Integration of strained Ge into advanced CMOS technology Integration of strained Ge into advanced CMOS technology

2007-07-17

2007-07-17

Nadav, Ori (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257S018000, C257S192000, C257S616000

Reexamination Certificate

active

10876155

ABSTRACT:
A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.

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