Integration of low dielectric material in semiconductor...

Details Integration of low dielectric material in semiconductor... Integration of low dielectric material in semiconductor...

1999-12-17

2003-12-02

Cuneo, Kamand (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C438S106000, C438S622000

Reexamination Certificate

active

06657302

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to provision of low RC time constant characteristics in semiconductor interconnection schemes. More specifically, the invention relates to integrated circuit designs and methods of applying insulative materials having low dielectric constants in order to reduce capacitance between conductive lines in such circuit designs.
BACKGROUND OF THE INVENTION
As semiconductor process integration progresses the density of multilevel interconnection schemes continues to increase. At the same time the aggregate amount of interconnect on microprocessors and other complex integrated circuits continues to escalate. In fact, semiconductor interconnect requirements are considered one of the most demanding aspects of ultra large scale integration efforts. Among other concerns, it is becoming more difficult to sustain acceptable electrical performance as devices of growing complexity are manufactured at smaller geometries. Specifically, the speed of signals propagating on interconnect circuitry vary inversely with line resistance and capacitance.
With feature sizes and spacings becoming smaller, the speed of an integrated circuit depends less on the switching device characteristics and depends more on the electrical properties of the interconnect structure. Conductors providing lower resistivity are desired in order to increase current density and insulators having lower dielectric constants are needed to reduce capacitance. Thus there is some motivation to not use Al interconnect and silicon dioxide insulator. (Silicon dioxide deposited by chemical vapor deposition has a dielectric constant of 4.0 or higher, depending on moisture content.) It is becoming necessary to apply new materials, e.g., metals having better conductive properties and insulators having lower dielectric constants, in order to maintain and improve electrical performance characteristics. In particular, efforts to reduce RC time delays and capacitive coupling have resulted in greater use of silicides and copper metalization schemes as well as the so called “low k” dielectrics, the latter being insulative materials characterized by relatively low dielectric constants relative to silicon dioxide. Nonetheless, RC delay and capacitive coupling are recognized as significant limiting factors affecting high frequency circuit performance.
With regard to low k dielectrics, as geometries have extended below the 0.25 micron regime and move toward 0.1 micron, the thermal and mechanical properties of these materials are of limited compatibility with current manufacturing processes. For example, due to desired porosity which helps decrease the dielectric constant, the mechanical properties are not well-suited for chemical-mechanical polishing (CMP). That is, the dielectric material, which is typically spun-on (in the case of polymers) or deposited (if inorganic), is relatively soft or flaky such that there is insufficient control during the polish step. Known accommodations include depositing more rugged cap dielectrics over the low k material in order to utilize established process equipment. For example, hydrogen silsesquioxane (k=3, approx.), a strong candidate for replacing silicon dioxide, has high thermal stability, excellent gap-fill properties, and low current leakage. Nonetheless, because the material is not suitable for standard CMP, volume manufacture has required that an overcoat of silicon dioxide formed by Plasma Enhanced Chemical Vapor Deposition (PECVD) be applied prior to the CMP operation and polishing is limited to this cap layer. Use of cap material permits CMP processing but this is considered sub-optimal for high performance circuitry. The cap oxide, having a significantly higher dielectric constant, can influence some electrical circuit properties. Elimination of cap oxide will provide improved circuit performance.
More generally, efforts continue to apply insulators having even lower dielectric constants (approaching k=1.5). The two most important properties for successful implementation of such materials in processes below 0.2 micron are considered to be adhesion (to dissimilar materials) and mechanical toughness (for CMP). Certain forms of hydrogen silsesquioxane can exhibit dielectric constants of approximately 1.5 by controlling the void volume. They also exhibit relatively good adhesion to other materials such as metal bond pads and differing dielectric materials. Of course these favorable results may depend largely on optimized process conditions, e.g., the satisfactory cleaning of surfaces prior to formation of the dielectric thereon, but they appear attainable. In contrast to the advancements made in performance and materials compatibility, manufacturable solutions which accommodate the mechanical properties of low k dielectrics have been generally limited to provision of oxide cap polishing layers. A different approach, which does not require polishing of the low k dielectric material nor the provision of a relatively hard cap layer thereon, will simplify manufacture of multi-level interconnect schemes.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a solution to the aforementioned problems begins with provision of an insulator material between interconnect members, followed by replacement of the insulator material with a dielectric material having a lower dielectric constant.
Generally, the invention enables relatively simple and cost efficient placement of insulative material having a low dielectric constant between interconnect members of a circuit structure. According to the invention, the structure is etched to remove oxide between or above conductive members. Utilization of an anisotropic etch assures that portions of the oxide are left in place, aligned with interconnect members.
A circuit structure fabricated accordingly has a first level of interconnect members formed over a semiconductor layer and a lower level of interconnect members formed between the semiconductor layer and the first level of interconnect members. An insulative material such as silicon dioxide electrically isolates interconnect members of the lower level from devices formed along the semiconductor surface while a different insulative material, e.g., a low k dielectric such as hydrogen silsesquioxane, electrically isolates interconnect members of the first level from one another.
The foregoing background and summary have outlined general features of the invention. Those skilled in the art may acquire a better understanding of the invention and the preferred embodiments with reference to the drawings and detailed description which follow.


REFERENCES:
patent: 5548159 (1996-08-01), Jeng
patent: 5744865 (1998-04-01), Jeng et al.
patent: 5783864 (1998-07-01), Dawson et al.
patent: 5818111 (1998-10-01), Jeng et al.
patent: 5858871 (1999-01-01), Jeng
patent: 5976984 (1999-11-01), Chen et al.
patent: 6054769 (2000-04-01), Jeng

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