Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-18
2001-09-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000, C438S416000
Reexamination Certificate
active
06284581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to BiCMOS transistor devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,793,085 of Vajana et al. for “Bipolar Transistor Compatible with CMOS Processes” shows a BiCMOS process with ion implanted source/drain and base regions.
U.S. Pat. No. 5,681,765 of Darmawan for “Process for Fabricating Single Polysilicon High Performance BiCMOS” shows a BiCMOS processes with a patterned photoresist layer 80 with an opening above a polysilicon layer 78 with a thickness of about 3250 Å. Dopant 44 is implanted through the opening in the photoresist layer to form a base-emitter region 84 for an eventual bipolar transistor in a tub 68 in an epitaxial layer 60.
U.S. Pat. No. 5,606,192 of Harada for “Semiconductor Integrated Circuits Having Bipolar Transistors and LDD-Structured MOSFET” show BiCMOS processes with polysilicon layers and ion implanting boron ions to form an N-type region in a polysilicon emitter electrode layer 23 formed above a gate oxide layer 12, which in turn is formed above a base layer 19 formed in an N-type epitaxial layer 4 in a P-silicon substrate 1.
U.S. Pat. No. 4,902,639 of Ford for “Process for Making BiCMOS Integrated Circuit Having a Shallow Trench Bipolar Transistor with Vertical Base Contacts” describes a BiCMOS process, but makes a reference to the NMOS region 27 at Col. 3, lines 23-41, to an intermediate stage of manufacturing the NMOS region 27. A second polysilicon layer is deposited on a previous polysilicon layer. The second polysilicon layer is then heavily doped to become a poly-silicon N+ layer with an N+ dopant. Alternatively the polysilicon is deposited as a heavily doped layer by an in situ process. Then in NMOS region 27, using a portion of the second polysilicon layer which is now heavily doped polysilicon N+ layer 40, a buried contact region 41 is formed in a P-well region 16 by diffusion, as the result of a high temperature anneal. In Col. 4, lines 4-43, a trench is formed where the NPN transistor is to be formed. First an active base region 67 is formed by implanting boron in the N-well 19. Oxide sidewalls 68 are formed in the trench. A polysilicon emitter 69 is deposited in the trench between the oxide sidewalls 68. Then emitter 69 is doped N-type using masks and implants. By this process or an anneal, a very shallow N-type emitter junction is formed in the active base region from the doping of the polysilicon emitter 69.
U.S. Pat. No. 5,504,362 of Pelella et al., “Electrostatic Discharge Protection Device” in Cols. 7 and 8 and FIG. 2 teaches out diffusion from N+ polysilicon emitter contact 48/P+ polysilicon base contact 44 to form N+ emitter out diffusion region 39/P+ base out diffusion region 40 of an NPN bipolar transistor 15C in a BiCMOS device.
U.S. Pat. No. 5,652,154 of Komuro for “Method for Manufacturing BiCMOS Device” shows a process for manufacturing a BiCMOS device. At Col. 5, lines 7-37, an intrinsic base region 109 is formed by ion implantation of a P-type dopant comprising boron into an N-type silicon region C of a P-type silicon substrate 101. Later in the process there is an ion implantation of the polysilicon layer which is first “ modified to have an N-type conductivity” by driving dopant from a doped glass layer or by ion implanting N-type dopant into the polysilicon. Then the doped polysilicon is formed into gate electrodes 112
a
-112
c
which are to be used to form FET devices in areas A and B and a bipolar device in area C. Then“. . . in area C, the polysilicon layer is left as an emitter electrode 112
c
above an emitter diffused region forming area for the bipolar transistor.” The next step is a heat treatment step employed to form an N-type emitter region 113 in the P type intrinsic region 109. (Col. 5, lines 38-59).
SUMMARY OF THE INVENTION
When the gates of CMOS transistors are scaled to less than 100 nm, the gate oxide thicknesses will be around 5 Å to 40 Å. Under such circumstances, the gate structures of bipolar devices and MOS devices become more similar than the large geometry devices.
In accordance with this invention, a simple approach to the method of manufacture and the structure of bipolar devices and MOS devices is provided. The proposed invention is very compatible with CMOS process with minimum additional steps to form the self-aligned bipolar transistors in a standard CMOS process.
In accordance with the method of this invention a semiconductor device is formed with dielectric, isolation structures in a top surface of a silicon semiconductor substrate, separating the substrate into a plug area, an emitter area, an NMOS area and a PMOS area. The plug area is juxtaposed with the emitter area away from the NMOS area and the PMOS area. Form a buried doped layer for a bipolar transistor in the plug area and the emitter area of the substrate deep below the surface. Form a collector plug region in the plug area, reaching from the surface of the substrate to reach the buried doped layer. Form a gate oxide layer superjacent to the isolation structures on the top surface of the silicon semiconductor substrate. Form a conductive polysilicon layer superjacent to the thin silicon oxide layer. Mask the NMOS and PMOS regions of the substrate with an emitter mask having a window over the emitter area of the substrate. Ion implant emitter dopant into a portion of the conductive polysilicon layer over the emitter area of the substrate through the window in the emitter mask. Strip the emitter mask. Anneal the substrate including the thin silicon oxide layer, and the polysilicon layer to drive the dopant into an emitter region in the emitter area in the substrate. Form doped source/drain regions and a base in the emitter area of the substrate. Preferably, the annealing is performed by rapid thermal annealing. The isolation structures are trenches formed in the substrate filled with silicon oxide dielectric. The gate oxide has a thickness from about 5 Å to about 40 Å.
REFERENCES:
patent: 4755487 (1988-07-01), Scovell et al.
patent: 4902639 (1990-02-01), Ford
patent: 5338696 (1994-08-01), Ilderem et al.
patent: 5504362 (1996-04-01), Pelella et al.
patent: 5606192 (1997-02-01), Harada
patent: 5652154 (1997-07-01), Komuro
patent: 5681765 (1997-10-01), Darmawan
patent: 5793085 (1998-08-01), Vajana et al.
Higashitani et al., “Submicron CBiCMOS Technology with New Well and Buried Layer Formed by Multiple Energy Ion Implantation”, IEEE Custom Integrated Circuits Conference, 1991, pp. 18.4.1-18.4.4.
Liu Erzhuang
Pan Yang
Chartered Semiconductor Manufacturing Ltd.
Jones, II George S.
Nguyen Tuan H.
Pike Rosemary L. S.
Saile George O.
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