Integration of biaxial tensile strained NMOS and uniaxial...

Details Integration of biaxial tensile strained NMOS and uniaxial... Integration of biaxial tensile strained NMOS and uniaxial...

2006-11-21

2006-11-21

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C257SE21129

Reexamination Certificate

active

07138309

ABSTRACT:
A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxial tensile strain, and the silicon layer in the PMOS active area is uniaxial compressive strained; and completing the CMOS device.

REFERENCES:
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Thompson et al.,A Logic Nanotechnology Featuring Strained Silicon, IEEE Electron Device Letter, vol. 25, No. 4, pp. 191-193 (2004).
Lee et al.,Fabrication of Strained Silicon on Insulator(SSOI)by Direct Wafer Bonding Using Thin Relaxed SiGe Film as Virtual Substrate, MRS Proceedings vol. 809, (2004).

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