Integration of a salicide process for MOS logic devices, and a s

Details Integration of a salicide process for MOS logic devices, and a s Integration of a salicide process for MOS logic devices, and a s

1999-05-12

2000-08-01

Fahmy, Wael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438257, 438210, 438275, H01L 218234

Patent

active

060965959

ABSTRACT:
A semiconductor fabrication process has been developed, allowing the integration of high performance MOS logic devices, and high density, MOS memory cell arrays, to be realized on the same semiconductor chip. The process features the use of two gate insulator layers, featuring different thicknesses, with the thinner of the two gate insulator layers, used for the high performance MOS logic devices. Two insulator spacers, featuring different thicknesses, are also employed, with the thinner spacer of the insulator spacers used on the sides of the polycide gate structures, to minimize memory cell area, while the thicker insulator spacers, on the sides of the polysilicon gate structures, in the MOS logic region, are used to allow a robust salicide procedure to be performed. In addition SAC openings, are used in the MOS memory region, for purposes of miniaturization, while salicide layers are used to improve the performance of MOS logic components.

REFERENCES:
patent: 5668359 (1997-09-01), Fang et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5792684 (1998-08-01), Lee et al.
patent: 5817562 (1998-10-01), Chang et al.
patent: 5998251 (1999-12-01), Wu et al.
patent: 6008081 (1999-12-01), Wu
patent: 6037222 (2000-03-01), Huang et al.

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