Integration method to enhance p+ gate activation

Details Integration method to enhance p+ gate activation Integration method to enhance p+ gate activation

2005-04-12

2005-04-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S526000, C438S585000, C438S529000, C438S785000

Reexamination Certificate

active

06878583

ABSTRACT:
A new process integration method is described to form heavily doped p+source and drain regions in a CMOS device. After defining the p- and n-well regions on a semiconductor substrate, gate silicon dioxide is deposited and nitrided in a nitrogen-containing atmosphere. Poly-silicon is then deposited and the two NMOS and PMOS gates are formed. For the p+doping of the poly-silicon gate and S/D regions around the PMOS gate, B+ions are then implanted. Cap dielectric layer comprising silicon dioxide is then deposited, followed by dopant activation with high temperature rapid thermal annealing. The cap dielectric layer is then used as resist protective film; it is removed from those areas of the chip that would require formation of electrical contacts. Silicide electrical contacts are then formed in these areas.

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