Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-18
2001-01-23
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S258000, C438S259000
Reexamination Certificate
active
06177318
ABSTRACT:
BACKGROUND OF THIS INVENTION
1) Field of the Invention
This invention relates to a fabrication method for an electrically programmable read-only, split gate MONOS (Metal/polysilicon Oxide Nitride Oxide silicon) memory having a composite of oxide-nitride-oxide (ONO) underneath the control gate in which high efficiency of channel hot electron injection from channel to silicon nitride can be achieved.
2) Description of the Prior Art
Side wall polysilicon gates with MONOS structure was reported by Kuo-Tung Chang et al in the paper “A New SONOS Memory Using Source Side Injection for Programming” in IEEE Electron Letter, Vol. 19, No. 7, July 1998. In the structure, a channel potential drop is formed at the gap between the sidewall gate and the select gate (word) such that the channel electron are accelerated in this gap region and become hot enough to inject into the oxide-nitride-oxide layer (trapped in the nitride layer) underneath the sidewall gate.
As shown in FIG.
1
a
, the typical sidewall process forms spacers on both sides of the word gate. This source side hot electron injection, which is commonly used in floating gate nonvolatile memory was first time employed for MONOS memory programming by Kuo-Tung Chang et al. In the similar structure, when the gate channel is reduced to less than 40 nm (Kuo-Tung Chang et al's channel length is about 200 nm), a new and much more efficient injection mechanism (Ballistic injection) takes over instead of source side injection as predicted in the S. Ogura U.S. Pat. No. 5,780,341. The ballistic injection mechanism has been proved by S. Ogura in the paper “Step Split Gate Cell with Ballistic Direct Injection for EEPROM/Flash” in IEDM 1998, pp. 987. As shown in FIG.
1
b
, when the control gate channel length is even 100 nm (Kuo-Tung Chang et al's channel length is twice as large that is 200 nm), the injection mechanism becomes source side injection which requires high floating gate potential above 5 volts. However, when the memory gate becomes less than 40 nm and the channel is properly doped, a ballistic injection device can be formed.
Because most of the embedded logic applications utilize only one side of polysilicon, one memory element word gate, the unused side spacer is removed or disabled. It is possible to disable the effect of unwanted side of control gate by implants of N− dopants such as Arsenic or Phosphorus under the unwanted gate using a block mask, prior to formation of the sidewall spacer, in order to short the unwanted gate to the adjacent diffusion. In another approach, the unwanted polysilicon gate material is used to fill the self aligned contact, as shown by Seiki Ogura in U.S. Pat. No. 5,780,341.
However, in integrating the Split Gate MONOS Transistor and high voltage devices in logic technology an optimum process which provides simplicity and reliability has to be considered. The logic gates, high voltage gates, and memory gates are all dimensionally critical and their relative positions are important. Therefore, it is preferable to define all three types of devices together at once rather than by separate masking processes. However, this preferred idea faces difficulty once the logic gate oxide becomes thin as 3.0 nm in the 0.18 micron feature size technology.
If the logic gates are formed prior to the side wall gates, the side wall spacers on the logic gates need to be removed, and the edges of the logic gate oxide could be damaged during the removal. On the other hand, if the logic gates are defined by a second critical mask after the memory word gates and spacer gates have been defined and formed, the damage to the logic gates' oxide during spacer removal, can be avoided. But the second approach requires two critical masks to define memory word gate and logic gate separately.
SUMMARY OF THE INVENTION
It is a principal object of this invention to (i) define controllably the ultra short channel, small size by sidewall technique for fast program at low voltage utilizing the Ballistic injection mechanism and (ii) define all three types of devices together at once rather than by separate masking processes.
It is a further object of this invention to form the sidewall polysilicon gate only on one side of the memory cell, but not to form the sidewall polysilicon gate on the logic and high voltage devices.
In the present invention, a new integration process is introduced, in which one critical mask is used to define all of the logic gates, high voltage devices, and the memory cells. But the side wall polysilicon gate is formed only on one side of the memory cell, where the MONOS control gate is wanted. Using a single critical mask step, simplifies the number of process steps and saves cost. An additional advantage of this process is the use of a logic gate side wall insulator, which protects the memory cells.
The channel length under the MONOS control gate is between preferably about 25 to 50 nm and is defined by first side wall spacer. The step edge is also defined by this first disposable side wall spacer, during step split transistor fabrication. The length of the N region is determined by the difference between the last polysilicon spacer and the first spacer thickness. The unique material selection and mask sequence allows formation of the side wall spacer gate on only one side of the split-word gate. Furthermore, logic gates are formed after forming of the sidewall MONOS control gates, thus protecting the delicate scaled complementary metal oxide semiconductor (CMOS) logic from the MONOS control gate process steps.
A fabrication method for an electrically programmable read-only memory device, which has high efficiency of electron injection from channel to silicon nitride layer is provided. This memory cell consists of a silicon word gate and a sidewall MONOS control gate on the sidewall of word gate. The MONOS control gate has an ultra short channel device formed by the double side wall spacer technique.
The uniqueness of this invention is to fabricate safely, the sidewall MONOS control gate involving double sidewall spacer process in the delicate scaled CMOS process environment, using the following techniques:
(1) a composite layer of thin silicon oxide layer and silicon nitride layer on normal gate polysilicon are defined at once for logic, high voltage and memory devices. Using another block mask, only one side of the memory gate is etched, where the MONOS control gate spacer should be formed.
(2) Disposable sidewall spacer forms only on the etched side of polysilicon layer, and defines the ultra short channel of between about 25 to 60 nm by blocking implant of arsenic N dopant by disposable spacer, in order to provide low voltage and high speed Channel Hot Electron (CHE) programming.
(3) The disposable sidewall spacer can be polysilicon, or doped polysilicon (which provides high etch rate compared to lightly doped silicon), or plasma deposited silicon oxynitride (which provides high etch rate compared to thermal silicon oxide) or chemical vapor deposited borophophosilicate glass.
(4) The final MONOS control gate is formed on only one side of word gate transistor, in both the flat channel and step channel processes.
(5) Logic gates are defined after formation of the memory devices. In embedded nonvolitile memory, such as nonvolitile randon access memory (NVRAM) or logic applications, the transistor count of logic is much higher than flash memory transistors, and the thinner silicon oxide logic devices are more delicate. Therefore, it is important to finish MONOS memory cell prior to logic device formation.
(6) Furthermore, all of the devices are defined by the original single critical mask.
(7) Logic spacer insulator is utilized to protect the memory cells.
REFERENCES:
patent: 5494838 (1996-02-01), Chang et al.
patent: 5496753 (1996-03-01), Sakurai et al.
patent: 5776787 (1998-07-01), Keshtbod
patent: 5780341 (1998-07-01), Ogura
patent: 5789297 (1998-08-01), Wang et al.
patent: 5824584 (1998-10-01), Chen et al.
patent: 5851881 (1998-12-01), Lin et al.
patent: 5930631 (1999-07-01), Wang et a
Hayashi Yutaka
Ogura Seiki
Ogura Tomoko
Ackerman Stephen B.
Booth Richard
Halo LSI Design & Device Technology, Inc.
Pike Rosemary L.S.
Saile George O.
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