Integration method for sidewall split gate flash transistor

Details Integration method for sidewall split gate flash transistor Integration method for sidewall split gate flash transistor

1998-10-30

2000-06-13

Smith, Matthew

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438593, H01L 21336

Patent

active

060749148

ABSTRACT:
A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

REFERENCES:
patent: 5278087 (1994-01-01), Jenq
patent: 5780341 (1998-07-01), Ogura
patent: 5879993 (1999-10-01), Chien et al.
patent: 5966601 (1999-10-01), Ling et al.
patent: 5981341 (1999-11-01), Kim et al.
Y. Yamauchi, "A 5V-Only Virtual Grand Flash Cell with An Auxiliary Gate for High Density and High Speed Application" IEDM, 1991, pp. 319-322.

Affiliated with

Also associated with

Rating

Integration method for sidewall split gate flash transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integration method for sidewall split gate flash transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integration method for sidewall split gate flash transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2067957