Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2006-09-28
2008-11-25
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S190000, C365S189070
Reexamination Certificate
active
07457171
ABSTRACT:
During a read access to a memory cell array of an integrated semiconductor memory device, data of a data word is fed to a data generator circuit which can be operated in the operating modes of noninverted and bitwise inverted transmission of data. The data generator circuit generates a control signal at a control terminal dependent on the transmission mode. The data generator circuit compares a data word fed to it from the memory cell array, with a data word fed to it from the memory cell array one clock period previously. The present operating mode of the data generator circuit is changed if more than half of the data of the two data words that are fed are different. Otherwise, the operating mode is maintained. It is thereby possible to reduce the number of data changes during a read access and thus the power loss of a data interface.
REFERENCES:
patent: 7106654 (2006-09-01), Kock et al.
patent: 2002/0071331 (2002-06-01), Al-Shamma et al.
patent: 2005/0157586 (2005-07-01), Kock et al.
patent: 2006/0149989 (2006-07-01), Marx et al.
Edell Shapiro & Finnan LLC
Qimonda AG
Tran Andrew Q
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