Integrated semiconductor memory with redundant memory cells...

Details Integrated semiconductor memory with redundant memory cells... Integrated semiconductor memory with redundant memory cells...

2007-06-26

2007-06-26

Nguyen, VanThu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189050, C365S189070, C365S190000

Reexamination Certificate

active

11053659

ABSTRACT:
An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

REFERENCES:
patent: 5218572 (1993-06-01), Lee et al.
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5963489 (1999-10-01), Kirihata et al.
patent: 6292383 (2001-09-01), Worley
patent: 6608783 (2003-08-01), Frankowsky et al.
patent: 2004/0001375 (2004-01-01), Beer

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