Integrated semiconductor memory device utilizing a test circuit

Details Integrated semiconductor memory device utilizing a test circuit Integrated semiconductor memory device utilizing a test circuit

1992-02-28

1994-09-27

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 257359, 257381, 257385, G11C 1300

Patent

active

053512138

ABSTRACT:
A semiconductor memory device of the type having a test circuit incorporated integrally therewith generates test data to be batch written into the device's memory cells. The memory device includes at least one memory block to which there may be connected sense amplifiers through which read/write operations can be effected. A test circuit is also provided which function is to test each memory block. A peripheral circuit is formed electrically connected to any memory blocks. Accordingly, memory blocks as well as the peripheral circuit are formed on a semiconductor substrate onto which there is formed a `single` layer having both high (undoped thin poly-Si current paths-108CH) and low (doped thin poly-Si joint path-108SD) resistivity regions therein. The inherent properties of the undoped high-resistivity current paths 108 CH are such that in response to control signals from control gate electrodes, an electrical conductance of the current paths can be altered. The resultant structure yields improvements in manufacturing costs, test time and ancillary costs associated with memory block testing.

REFERENCES:
patent: 4604641 (1986-08-01), Konishi
patent: 4792841 (1988-12-01), Nagasawa et al.
patent: 5060230 (1991-10-01), Arimoto et al.
patent: 5088063 (1992-02-01), Matsuda et al.
SDM 89-31: A Memory Architecture for 16Mb DRAMs (published on Jun. 21, 1989).
SDM 89-32: A 55ns 16Mb DRAM with Built-in-Self-Test Function Using Micro-Program ROM (published on Jun. 21, 1989).
SDM 90-199: A 64Mbit DRAM with Merged Match-line Test Architecture (published on Mar. 27, 1991).

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