Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-07-15
2004-06-15
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S387000, C438S195000, C257S302000, C257S307000
Reexamination Certificate
active
06750098
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating an integrated semiconductor memory having memory cells with vertical transistors, which are formed at webs of a semiconductor substrate, and to such an integrated semiconductor memory.
Dynamic integrated semiconductor memories have a cell array with a multiplicity of memory cells each having a storage capacitor (a trench capacitor or a stacked capacitor) and a selection transistor in each case. In order to increase the memory cell density on a semiconductor substrate, vertical transistors are desirable as selection transistors for scaling reasons. In the case of a vertical field-effect transistor (MOSFETs; metal oxide semiconductor field-effect transistor), the channel region runs perpendicularly to the substrate surface.
The vertical selection transistors are often introduced within the trenches for the storage capacitors extending deep into the substrate. In this case, the selection transistors are disposed in an upper region of the trenches and connected to one another parallel to the substrate surface by word lines and bit lines.
In a less widely used configuration of a semiconductor memory, the vertical transistors are disposed outside the trenches, to be precise at webs, that is to say vertical pillars of the substrate material, which are formed by patterning the substrate surface. The patterning gives rise to a two-dimensional configuration of webs that are isolated from one another by trenches in the semiconductor substrate. Each web serves to form a respective selection transistor and is disposed laterally beside the trench of a storage capacitor. An outdiffusion of a doped material that is conductively connected to the inner electrode of the capacitor is produced at one of the four sidewalls of the web. A lower source/drain electrode is thus formed. A gate electrode in the form of a cladding running around all four sidewalls of the web is formed above the lower source/drain electrode. The gate electrode is formed after the production of a gate oxide layer by a conductive material being deposited conformally and isotropically onto the semiconductor substrate, which has been covered with the gate oxide layer and patterned to form webs, and subsequently being etched back anisotropically in a direction perpendicular to the substrate surface, for example by dry etching (RIE; reactive ion etching). This results in a gate electrode that is in the form of a spacer and surrounds an individual web. In the course of the anisotropic etching-back, during which the top side of the web is protected by a first insulation layer, upper regions of the sidewalls of the web are uncovered. The upper source/drain implantations are later introduced in the upper, uncovered region of the webs by a preferably angled implantation. A vertical selection transistor is thus produced in each web.
The selection transistors formed in this way are connected to one another by bit lines and word lines. Gate electrodes are connected to one another by the word lines. Since the gate electrodes are in the form of a spacer having a small layer thickness at the sidewalls of the webs, it is difficult to make contact with them. The gate electrodes that are in the form of spacers and are to be connected by the word lines are situated in a lower region of the sidewalls of the webs. In the course of the gate electrodes being contact-connected by the word lines, it is necessary to bridge a large height difference. At the same time, it is necessary to prevent the substrate material in the upper region of the webs or the bit lines from being contact-connected in the course of the contact-connection of the gate electrodes. Such critical contact-connection can often only be realized with additional patternings, i.e. lithography steps for forming the contacts, and is also problematic because the gate electrodes to be contact-connected have a small layer thickness.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor memory and a fabrication method that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which a semiconductor memory of the above-described configuration can be fabricated without the aid of additional lithographic patterning. Moreover, in the course of the contact-connection of the gate electrodes, the intention is to prevent inadvertent contact-connection of substrate material in the webs above the gate electrode or of bit lines.
Furthermore, the object of the present invention is to provide a semiconductor memory which can be fabricated in this way without additional lithographic patterning and without the risk of a short circuit between the gate electrodes and the substrate material or bit lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an integrated semiconductor memory having memory cells with vertical transistors. The method includes the steps of providing a semiconductor substrate, depositing a first insulation layer on the semiconductor substrate, and patterning the semiconductor substrate for producing a configuration of elongate webs extending principally in a first direction and formed from a material of the semiconductor substrate and of the first insulation layer. The elongate webs are laterally isolated from one another by trenches formed in the semiconductor substrate during the patterning. A gate oxide layer is then conformally deposited and gate electrodes are produced running around the elongate webs and disposed at a level of a lower region of sidewalls of the webs on the gate oxide layer. The trenches are filled with a first insulating material, and bit lines are formed above the elongate webs. The bit lines cross the elongate webs perpendicularly to the first direction and are conductively connected to top sides of the elongate webs. At least the top sides of the bit lines are covered with a second insulation layer. A second insulating material is deposited and further trenches are etched for forming word lines. The further trenches run parallel to the first direction, and the gate electrodes are uncovered at least in an upper region due to the etching. An isotropic, conformal deposition process is performed for forming a third insulation layer having a thickness less than a layer thickness of the gate electrodes on the gate oxide layer. The third insulation layer is anisotropic etched perpendicularly to a surface of the semiconductor substrate, thereby uncovering top sides of the gate electrodes. Then, word lines are produced running above the bit lines over the elongate webs parallel to the first direction and making contact with uncovered top sides of the gate electrodes.
According to the invention, an insulation layer which is thinner than the peripheral gate electrodes is produced, so that the gate electrodes project laterally beyond that region of the insulation layer which covers the sidewall above the gate electrodes. This layer thickness difference in the lateral direction enables the gate electrodes to be contact-connected exclusively from their smaller dimension, even though the sidewalls of the spacers are covered by the third insulation layer.
The etching of the third insulation layer directed perpendicularly to the substrate surface does not attack sidewalls of the webs above the gate electrodes and sidewalls of bit lines, but does potentially attack their top sides. However, the latter are protected, according to the invention, by the first and second insulation layers, thus enabling selective uncovering exclusively of the gate electrodes. The gate electrodes can be contact-connected there by the word lines running above the webs and the bit lines. The top sides of the webs and of the bit lines, by contrast, still remain protected.
The method according to the invention has the advantage that it can be combined with a folded bit line concept, in which a memory cell is provided only at
Manger Dirk
Schlösser Till
Everhart Caridad
Lee Calvin
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