Integrated semiconductor memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S704000

Reexamination Certificate

active

11123221

ABSTRACT:
An integrated semiconductor memory includes a memory cell array with at least one memory cell, in which a data value is stored, and an evaluation circuit with a counter. During a test of the integrated semiconductor memory, a counter reading of the counter is altered if the data value stored in the memory cell deviates from a desired value. A threshold value is predefined by a control circuit. A programming circuit compares the threshold value on the input side with the instantaneous counter reading of the counter. If the counter reading of the counter exceeds the threshold value, a programming element changes from a first programming state to a second programming state. After the conclusion of the test, the state of the programming element is read out via an output terminal. This scheme makes it possible to deduce a possible cause of failure of the integrated semiconductor memory.

REFERENCES:
patent: 5640354 (1997-06-01), Jang et al.
patent: 6295237 (2001-09-01), Pochmuller
patent: 6539506 (2003-03-01), Lammers et al.
patent: 6684353 (2004-01-01), Parker et al.
patent: 6829181 (2004-12-01), Seitoh

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