Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-02-05
2001-10-16
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S203000, C365S189011
Reexamination Certificate
active
06304491
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated semiconductor memory having memory cells for storing data signals, having a sense amplifier, a signal line and a memory circuit.
More recent generations of integrated semiconductor memories have an increasing integration density and an increasing number of integrated functions. A semiconductor memory is usually connected to further components which together form a computer system, for example. For semiconductor memories which have relatively large dimensions and relatively long conductor tracks it is becoming more and more difficult to achieve the data access times which are required by components which switch at high speed, for example the computer system.
A data access can usually be divided into a plurality of function blocks. In a first function block, access commands are decoded and the respective memory cell address generated. In a semiconductor memory which has, for example, a memory cell field in the form of a matrix, the column addresses are decoded in a second function block, a respective column line is selected by means of a column selection signal, and the data to be read out are amplified in a memory sense amplifier and transmitted outside of the memory cell field. There, they are usually fed to a further memory sense amplifier. In a third function block, a data signal which is to be read out is transmitted by this memory sense amplifier to an internal memory circuit or to an output buffer of the integrated memory, for example.
To enable a data signal which is to be read out to be transmitted to an internal memory circuit or an output buffer it is possible, for example, to use a data line pair with states which are differential with respect to one another. Here, one of the two lines has a signal crossover in each read cycle. As soon as the crossover is saved in a memory circuit, appropriate charging of the respective other line takes place in a known manner. This configuration requires a comparatively large amount of space on the semiconductor memory.
The data signal which is to be read out can alternatively be transmitted on a single static data line. This signal line, which connects the memory sense amplifier and either the internal memory circuit or the output buffer, has at most one signal crossover for each read cycle. In order to obtain the shortest possible access times, it is necessary to optimize both types of signal crossovers (for example “log. 0”=L to “log. 1”=H, “log. 1”=H to “log. 0”=L) in terms of their switching times. The minimum access time is limited here to the slower signal crossover of the two signal crossovers.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor memory which overcomes the above-mentioned disadvantageous of the prior art memories of this general type. The integrated semiconductor memory has a circuit configuration for reading out data signals that requires as little space as possible and that has comparatively high switching speeds for signal crossovers of the data signals to be read out.
With the foregoing and other objects in view there is provided, in accordance with the invention an integrated semiconductor memory that includes a plurality of memory cells. Each one of the memory cells is for storing a data signal. A memory sense amplifier is provided which has an input for receiving the data signal from one of the plurality of memory cells and has at least one output for providing an output signal. A driver circuit is provided which has an output and which has an input connected to the output of the memory sense amplifier. The driver circuit is capable of being activated or deactivated only by the output signal of the memory sense amplifier. A signal line is connected to the output of the driver circuit. A precharging circuit is connected to the signal line. A memory circuit is provided which has an input connected to the signal line and has an output. A terminal is provided for receiving a control signal. The terminal is connected to the memory sense amplifier, the precharging circuit and the memory circuit.
In accordance with an added feature of the invention, there is provided a terminal for receiving a first supply potential, and the driver circuit includes a transistor having a control path connected between the signal line and the terminal for receiving the first supply potential. The transistor of the driver circuit has a control terminal connected to the input of the driver circuit.
In accordance with an additional feature of the invention, there is provided a terminal for receiving a second supply potential, and the precharging circuit includes a transistor having a control path connected between the signal line and the terminal for receiving the second supply potential. The transistor of the precharging circuit has a control terminal connected to the terminal for receiving the control signal.
In accordance with another feature of the invention, the memory sense amplifier includes a further output for providing an output signal, and the integrated semiconductor memory further includes a logic processing unit having an output connected to the control terminal of the transistor of the precharging unit. The logic processing unit has an input connected to the terminal for receiving the control signal and has another input connected to the further output of the memory sense amplifier.
In accordance with a further feature of the invention, the memory sense amplifier includes a further output for providing an output signal, and the integrated semiconductor memory further includes a holding circuit that includes a transistor having a control path connected between the signal line and the terminal for receiving the second supply potential. The transistor of the holding circuit has a control terminal connected to the further output of the memory sense amplifier.
In accordance with another added feature of the invention, the data signal from the one of the plurality of the memory cells is formed from data selected from the group consisting of a data item having a first logic state and a data item having a second logic state, and the output signal from the at least one output of the memory sense amplifier defines a first output signal having a first state and a second state. The first state indicates that the data item having the first logic state is being read out by the memory sense amplifier. The second state indicates that the data item having the first logic state is not being read out by the memory sense amplifier. The memory sense amplifier includes an additional output providing an output signal defining a second output signal having a first state and a second state. The first state indicates that the data item having the second logic state is being read out by the memory sense amplifier. The second state indicates that the data item having the second logic state is not being read out by the memory sense amplifier.
In accordance with another additional feature of the invention, there is provided, a plurality of identical memory sense amplifiers, only one of the plurality of the memory sense amplifiers being activated at a time; and a plurality of driver circuits, each one of the plurality of the driver circuits connected to the signal line and assigned to a respective one of the plurality of the memory sense amplifiers.
In accordance with yet an added feature of the invention, there is provided, a decoder that is connected to the plurality of the memory sense amplifiers. The plurality of the memory cells are combined to form units of column lines and row lines. The decoder is for selecting one of the column lines.
In accordance with yet an additional feature of the invention, the control signal is a regular clock signal.
In accordance with yet a further feature of the invention, the integrated semiconductor memory is embodied as a dynamic semiconductor memory.
In accordance with a concomitant feature of the invention, the integrated sem
Johnson Bret
Kaiser Robert
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Mai Son
Stemer Werner H.
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