Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-30
2002-08-27
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S358000, C257S360000, C257S361000
Reexamination Certificate
active
06441437
ABSTRACT:
BACKGROUND OF THE INVENTION
FILED OF THE INVENTION
The invention lies in the field of semiconductors. The invention relates to an integrated semiconductor circuit with a protective structure for protection against electrostatic discharge.
Semiconductor circuits integrated in a chip contain protective circuits for protecting the inputs or outputs (I/O ports) against electrostatic overvoltages and electrostatic discharges (ESD). The ESD protective elements are connected between the input pad of an integrated semiconductor circuit and the input or output terminal to be protected. Consequently, the ESD protective elements ensure that when a parasitic overvoltage is coupled, the in ESD element is turned on and the parasitic overvoltage pulse is conducted away to one of the supply voltage conductive tracks. Such overvoltage pulses can lead, in the extreme case, to the destruction of the component. An ESD protective element is disclosed in European Patent Application 0 414 934 A1.
Under operating conditions described, for example, in a product specification, the ESD protective elements must not adversely affect the function of the integrated semiconductor circuits to be protected. In other words, the turn-on voltage of the ESD protective elements must lie outside the signal voltage range of the protected terminal pads. In order to develop a good protective action, the ESD protective element should break down before the most critical circuit path. As a rule, proper break down requires an exact setting of the turn-on voltage of the respective ESD protective elements with the essential boundary condition that the process control (which has been optimized with regard to the properties of the components of the integrated semiconductor circuit to be protected) is not altered by the insertion of the ESD protective elements.
A further essential boundary condition results from the spatial configuration of the terminal pads in immediate proximity to the integrated semiconductor circuit to be protected. In particular, the terminal pads are disposed in the vicinity of the output drives due to the relatively high currents to be driven. The ESD protective structure is, therefore, frequently connected to that supply line from which the output driver is supplied.
What is essential to the functioning of generic type ESD protective elements is the capability of allowing short high-current pulses right into the ampere range to be conducted away without the ESD element being damaged by the high-current pulses. The protective elements are operated in the event of breakdown during the ESD pulse. Because the protective elements have to be provided at all supply and signal terminals, they must be configured to be as compact and space-saving as possible. At the same time, the current to be conducted away must be distributed as uniformly as possible over the entire breakdown path. Uniform distribution obtains the highest possible total current through the protective element and, hence, a high ESD strength up to a critical current density that can lead to damage to the protective element (second breakdown).
Particularly, in the case of protective elements having a snapback behavior of the characteristic curve in the event of breakdown (e.g. bipolar transistors or thyristors), there is a risk that a location on the breakdown path or a finger of a multifinger structure triggers and conducts away the current without the remaining regions of the breakdown structure or the remaining fingers turning on. The protective elements and the integrated circuits to be protected that are connected downstream are often destroyed as a result of the effect.
Occasionally, very large potential differences in the base zone of the protective elements are the cause of such an inhomogeneous turn-on. These potential differences result from the very high sheet resistance of the base and the high currents to be conducted away. As a rule, an improvement can be obtained only by a suitable metallic interconnection of the base regions, in particular, finger structures. However, such interconnection requires contact to be made with the base regions, such contact being associated with a high outlay in terms of area. Moreover, the degree of homogenization that can be attained will differ greatly depending on configuration stipulations and technological parameters.
With regard to further details, features, advantages and method of operation of the ESD protective circuits, European Patent Applications 0 623 958 A1 and 0 414 934 A1 are incorporated by reference.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated semiconductor circuit with a protective structure for protection against electrostatic discharge that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that provides an ESD protective structure that has a distinctly improved homogenization of the current flow in the event of breakdown.
With the foregoing and other objects in view, there is provided, in accordance with the invention, in a semiconductor assembly having at least one semiconductor body, an integrated semiconductor circuit disposed in the at least one semiconductor body, an electrically conductive connecting line, at least one terminal pad connected to the integrated semiconductor circuit through the connecting line, at least one first busbar carrying a first supply potential of the integrated semiconductor circuit during operation, at least one second busbar carrying a second supply potential of the integrated semiconductor circuit during operation, and a protector for protecting the integrated semiconductor circuit against electrostatic discharge, the protector disposed between the at least one terminal pad and the integrated semiconductor circuit and connected to at least one of the at least one first busbar and the at least one second busbar, the protector including at least one protective element having first transistors each having a base terminal, a collector terminal, and majority charge carriers of a first conduction type, second transistors each having a base terminal, a collector terminal, and majority charge carriers of a second conduction type, the first transistors and the second transistors respectively connected by reciprocal coupling of at least one of the base terminals and the collector terminals to form a thyristor structure, at least one first integrated resistor with a lowest possible resistance driving the base terminals of the second transistors and the collector terminals of the first transistors, and a buried layer having partial regions with a higher doping concentration than regions of the buried layer outside the partial regions.
Integrated vertical switching transistors are utilized as ESD protective elements. The bases of the switching transistors are driven by integrated driving transistors. Essentially, the current gain (base-collector gain) of the driving transistors is small enough to avoid the triggering of the parasitic thyristor—which results from the wiring of the switching transistors and of the driving transistors—with an undesirable snapback of the high-current characteristic curve at the sustaining voltage. The turn-on voltage of the ESD protective element can be established advantageously by a suitable selection of the base widths of the driving transistors.
A buried layer configured to have the lowest possible resistance is essential to the invention. The sheet resistance of the buried layer defines an integrated resistor that is disposed between the base terminals of the driving transistors and the collector terminals of the switching transistors, and which enables homogenization of the current flow in the event of breakdown.
In accordance with another feature of the invention, the partial regions are disposed next to one another and/or are spaced apart from one another in the buried layer.
In accordance with an additional feature of the invention, there is provided a further partial region having at least one base zone, at least o
Chaudhuri Olik
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Nguyen Dilinh
LandOfFree
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