Integrated self aligned contact etch

Details Integrated self aligned contact etch Integrated self aligned contact etch

1998-07-09

2001-12-11

Kunemund, Robert (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000, C438S743000, C438S744000

Reexamination Certificate

active

06329292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to plasma etching in the fabrication of integrated circuit structures and, in particular, to an integrated plasma etch process module that includes a self aligned, selective oxide etch, nitride removal with high selectivity to corner nitride and stripping of all polymer and photoresist.
2. Description of the Related Art
Advanced integrated circuits include multiple conductive layers that are separated from a silicon substrate and from each other by intervening dielectric material. Contact or via holes are etched through the dielectric material and filled with a conductor to selectively provide electrical contacts or interconnects between the substrate and the various conductive layers.
While the dielectric layers in these integrated circuit structures can consist of a single layer of material, such as silicon oxide, more typically the dielectric layer includes an upper layer (e.g. silicon oxide) and a lower stop layer (e.g. silicon nitride with upper oxide). The stop layer has a composition relative to the upper layer such that a carefully chosen etch process that is selective to the material of the stop layer etches through the upper dielectric but stops on the stop layer, thus protecting the underlying material during the oxide etch. A further etch of the stop layer is then performed to expose the underlying material to complete the contact or via hole.
FIG. 1A
shows an integrated circuit structure commonly utilized in dynamic random access memory (DRAM) devices. The illustrated structure includes a silicon substrate
10
and two polysilicon gate electrodes
12
. The gate electrodes
12
are electrically insulated by surrounding silicon dioxide
14
which also separates the gate electrodes
12
from the underlying substrate
10
. A silicon nitride liner
16
is formed over the gate oxide
14
and exposed surfaces of the substrate
10
between the gate electrodes
12
. An intermediate silicon oxide layer
18
is formed over the nitride liner
16
.
Referring to
FIG. 1B
, as part of the DRAM circuit fabrication, electrical contact is made with the substrate
10
between the gate electrodes
12
. To achieve this, a photoresist (PR) mask
20
having an opening
22
is provided on the intermediate oxide layer
18
to facilitate the etching of a contact hole through the oxide
18
and the nitride liner
16
to the substrate
10
. However, as shown in
FIG. 1B
by dashed lines, limitations on existing photolithography techniques can cause misalignment of the mask
20
such that the etch opening
22
is formed partially over the gate oxide
14
. As a result, as shown in
FIG. 1C
, if the selectivity of the oxide etch chemistry to nitride is too low, etching of the intermediate oxide
18
can result in removal of liner nitride
16
on the sidewalls
24
, and particularly on the shoulders
26
of the gate oxide. Etch-through of the nitride liner
16
at these points exposes the gate oxide
14
to the oxide etch environment, potentially resulting in shorts between the contact and the gate electrode
12
.
Thus, the selectivity of the oxide etch to nitride both at the relatively open floor of the contact hole and at the shoulders
26
of the hole is particularly crucial.
One widely utilized technology for oxide etching is the use of a fluorinated chemical etchant. During the oxide etch step, a fluorine-containing polymer is formed as a passivation material and functions as an etch stop to cover the underlying nitride, thereby increasing the oxide etch selectivity dramatically. Following oxide etching, the pattern-defining photoresist and the fluorine-containing polymer are removed.
While increased selectivity can be achieved using a highly polymerizing etch chemistry, the extensive polymerization may cause etch stop, particularly in high density DRAM devices in which the distance between gate electrodes is very small. Etch stop occurs when the sidewalls of the etched hole become so heavily polymerized that the polymer closes the hole and prevents further etching at the bottom of the hole. As a result, the process window for a self-aligned dielectric etch is often limited by the conflicting requirements of the oxide etch to maintain the nitride liner while continuing to open the oxide in the hole.
Furthermore, during stripping of the photoresist and the fluorine-containing polymer, free fluorine radicals are released into the plasma from the dissociation of the polymer residue. The photoresist stripping plasma, now including free fluorine released from the polymer residue, can deleteriously effect the device structure.
Therefore, any etch chemistry or parameters that provide high selectivity and large etch stopping margin are particularly attractive in oxide etching.
SUMMARY OF THE INVENTION
The present invention provides an integrated self-aligned contact etch process. The process steps include oxide etch with high oxide etch rate, integrated selective oxide etch and nitride liner removal with high selectivity to corner nitride and the ability to remove the bottom nitride liner, and stripping of all polymer and photoresist. C
4
F
8
and CH
2
F
2
are used for the high selectivity oxide etch step. The unique behavior of CH
2
F
2
in high density plasma allows polymer protection to form on the nitride corner/sidewall and, at the same time, to etch the bottom nitride.
The foregoing aspects of the present invention will become more readily appreciated and better understood by reference to the following detailed description which should be considered in conjunction with the accompanying drawings.


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Buckner et al., Organic Films as Anti-Reflective Coatings on Solar Cells, Solar Energy Materials, vol. 12, pp 131-136, 1985.

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