Integrated on-chip half-wave dipole antenna structure

Details Integrated on-chip half-wave dipole antenna structure Integrated on-chip half-wave dipole antenna structure

2001-03-19

2003-05-13

Phan, Tho (Department: 2821)

Communications: radio wave antennas

Antennas

Microstrip

C343S795000, C257S531000, C257S778000

Reexamination Certificate

active

06563464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to the field of formation of semiconductor devices having inductive and capacitive elements, and more specifically to a method for fabricating a half-wave dipole antenna structure using known semiconductor processing techniques.
2. Related Art
Semiconductor chips are continually being made smaller with the goals of increasing both device speed and circuit density. Miniaturized devices built within and upon a semiconductor substrate are spaced very closely together, and their packaging density continues to increase. As the packaging density increases, semiconductor chips are subject to electrical and physical limitations which stem from the reduced size of the areas available for their placement. Also, as products utilizing advanced electronics become more complex, they rely on larger numbers of semiconductor chips for their intended operation.
Underlying the complex nature of much sophisticated equipment is the need for communication between various semiconductor chips. As the space between chips available for signal conductor routing shrinks, the area available for communications conductors becomes increasingly limited while at the same time communications needs increase. One solution to this need for increased communications incorporates radio frequency signals for communicating within and between semiconductor chips.
At present, semiconductor chips commonly contain integrated circuits which operate at clock frequencies near the gigahertz (“GHz”, i.e., 10
9
Hertz) frequency range. These integrated circuits effectively utilize on-chip wiring techniques for communication between active and passive circuit elements.
However, in future integrated circuits, these clock frequencies are expected to extend high into the GHz range. At such frequencies, on-chip wiring techniques exhibit inductive, resistive and capacitive delays which may significantly impair circuit performance.
Therefore there is a need for alternative passive devices which can effectively improve the speed of electrical signal propagation through active and passive components. One such type of passive device is the type of antenna used in radio frequency (“RF”) communication. This kind of RF communication system can be adapted for use at the semiconductor chip level by utilizing antennae which are fabricated on the semiconductor chips themselves. For instance, at 15 GHz, the free space wavelength of an electromagnetic (“EM”) wave is approximately 2 cm. In a silicon chip, the permittivity can be as high as 12, with a resulting wavelength of approximately 6 mm. This translates into a ¼-wavelength antenna that is only 1.5 mm long. This antenna dimension is much smaller than projected semiconductor chip dimensions. Therefore, integration of antennae with the required receiver and transmitter circuits may become feasible, at frequencies in the GHz range, for intra- and inter-chip wireless communication. See, for example, “Characteristics of Integrated Dipole Antennas on Bulk, SOI, SOS Substrates for Wireless Communication”, Kihong Kim and Kenneth K. O, IITC 98-21, IEEE, 1998.
SUMMARY OF THE INVENTION
The invention disclosed herein presents an on-chip antenna apparatus that enables radio frequency (RF) communication between integrated circuits. A method for forming the antenna is also disclosed.
The present invention provides an antenna formed on a semiconductor structure, said semiconductor structure comprising: a substrate, containing electrical circuits operationally related to the functionality of the antenna; a first antenna element and a second antenna element formed on said substrate, wherein said first and second antenna elements each have a longitudinal axis and each of said longitudinal axes lies along substantially the same linear axis, and are separated by a gap; wherein each of said first and second antenna elements are in electrical contact with said electrical circuits; and wherein each of said first and second antenna elements are composed of solder bumps.
The present invention also provides a method of forming an antenna structure on a semiconductor substrate comprising the steps of: providing a semiconductor substrate; providing semiconductor devices fabricated within at least one layer of said semiconductor substrate; forming at least one solder bump antenna element on the semiconductor substrate; and forming at least one connecting device to electrically connect said solder bump antenna element and at least one of said semiconductor devices.
The present invention additionally provides a method of forming a phased antenna array of semiconductor chip antennae comprising: providing a plurality of semiconductor substrates; forming a plurality of on-chip solder bump antennae on said semiconductor substrates; and manipulating said plurality of on-chip solder bump antennae.
The present invention further provides a semiconductor packaging structure comprising: a semiconductor chip having an antenna formed on a first surface thereof; a plurality of electrical interconnects formed on the first surface; and a device for connecting to said semiconductor chip via said electrical interconnects, said device having structural refinements to operationally accommodate said antenna.
The foregoing and other features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention.


REFERENCES:
patent: 5185613 (1993-02-01), Whatmore et al.
patent: 5367308 (1994-11-01), Weber
patent: 5396658 (1995-03-01), Hwu et al.
patent: 5404581 (1995-04-01), Honjo
patent: 5541614 (1996-07-01), Lam et al.
patent: 5621913 (1997-04-01), Tuttle et al.
patent: 5629241 (1997-05-01), Matloubian et al.
patent: 5757074 (1998-05-01), Matloubian et al.
patent: 5786626 (1998-07-01), Brady et al.
patent: 5903239 (1999-05-01), Takahashi et al.

Affiliated with

Also associated with

Rating

Integrated on-chip half-wave dipole antenna structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated on-chip half-wave dipole antenna structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated on-chip half-wave dipole antenna structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3069651