Integrated non-volatile and random access memory and method of f

Details Integrated non-volatile and random access memory and method of f Integrated non-volatile and random access memory and method of f

1998-03-20

2000-09-26

Hardy, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438199, 438200, 438217, 438257, 438258, 438266, 438275, 438276, H01L 218238

Patent

active

061241571

ABSTRACT:
A method of forming non-volatile memory (e.g., an EEPROM device) and a CMOS device (e.g., a RAM), on a single die or chip, and a structure formed by the method. In one embodiment, the control gate of the storage transistor as well as the isolation gate of the isolation transistor may be formed during the same manufacturing process step, and thus may be formed of the same gate poly material and may have similar thickness.

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Wei-Hua Liu et al., A 2-Transistor Source-Select (2TS) Flash Eeprom For 1.8V-Only Applications, pp. 1-3.

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