Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2010-02-25
2011-10-11
Hoang, Quoc (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C257SE21619
Reexamination Certificate
active
08034677
ABSTRACT:
Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNxand the second nitride film is SiCNxwith a low wet etch rate in H3PO4and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
REFERENCES:
patent: 6706571 (2004-03-01), Yu et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 7190050 (2007-03-01), King et al.
patent: 7247887 (2007-07-01), King et al.
patent: 7265008 (2007-09-01), King et al.
patent: 7508031 (2009-03-01), Liu et al.
patent: 7528465 (2009-05-01), King et al.
patent: 7605449 (2009-10-01), Liu et al.
patent: 2004/0087133 (2004-05-01), Kumar
patent: 2005/0142735 (2005-06-01), Shin
patent: 2005/0153490 (2005-07-01), Yoon et al.
patent: 2006/0099762 (2006-05-01), Kim
patent: 2007/0037343 (2007-02-01), Colombo et al.
patent: 2007/0120156 (2007-05-01), Liu et al.
patent: 2007/0122953 (2007-05-01), Liu et al.
patent: 2007/0122954 (2007-05-01), Liu et al.
patent: 2007/0128782 (2007-06-01), Liu et al.
patent: 2007/0132053 (2007-06-01), King et al.
patent: 2008/0290470 (2008-11-01), King et al.
patent: 2008/0296632 (2008-12-01), Moroz et al.
patent: 2009/0181477 (2009-07-01), King et al.
patent: 2009/0206446 (2009-08-01), Russ et al.
patent: 2010/0035423 (2010-02-01), Clark
Gan Tian-Choy
Huang Wen-Sheh
Hung Chia-Lung
Lin Chia-Pin
Lin Hsien-Chin
Duane Morris LLP
Hoang Quoc
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
Integrated method for forming high-k metal gate FinFET devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated method for forming high-k metal gate FinFET devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated method for forming high-k metal gate FinFET devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4296075