Integrated method by using high temperature oxide for top oxide

Details Integrated method by using high temperature oxide for top oxide Integrated method by using high temperature oxide for top oxide

1999-10-25

2000-09-12

Booth, Richard

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438954, 438261, H01L 218247

Patent

active

06117730&

ABSTRACT:
A process for fabricating an ONO structure for a MONOS type Flash cell having a core and a periphery includes providing a semiconductor substrate. A first silicon oxide layer is grown overlying the semiconductor substrate, and a silicon nitride layer is deposited overlying the silicon oxide layer. Before depositing a second silicon oxide layer of the ONO structure, a bit-line mask is performed for forming at least one bit-line at the core. Thereafter, an ONO mask is formed to protect the ONO structure during an etch of the periphery. After depositing and cleaning the masks for the bit-line formation and the periphery etch, the second silicon oxide layer is deposited to overlie the silicon nitride layer using an HTO deposition process. By depositing the second silicon oxide layer after forming the ONO and bit-line masks, degradation of the second silicon oxide layer is prevented, and the top silicon oxide layer maintains a high quality.

REFERENCES:
patent: 5104819 (1992-04-01), Freiberger et al.
patent: 5907775 (1999-05-01), Tseng
patent: 6054734 (2000-04-01), Aozasa et al.

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