Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-05-24
2002-05-28
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S230060, C365S233100
Reexamination Certificate
active
06396755
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having a memory cell array. The memory cell array has column lines, row lines, and memory cells which are each connected to one of the row lines to select one of the memory cells and to one of the column lines to read or write a data signal. The integrated memory has a row access controller to activate one of the row lines to select one of the memory cells and to control a precharging operation to precharge one of the row lines. The invention also relates to a method of operating such a memory.
An integrated memory generally has a memory cell array which includes column lines and row lines. In this case, the memory cells are provided at crossing points of the column lines and row lines. In order to select one of the memory cells, the latter are in each case connected to one of the row lines. To this end, for example, a select transistor of respective memory cells is turned on by an activated row line, such that it is then possible for a data signal to be read from or written to a corresponding selected memory cell. To this end, the selected memory cell is connected to one of the column lines, via which the corresponding data signal is read or written.
In an inactive state, the row lines are normally precharged to a precharge potential. This means that, after a data signal has been read or written, the corresponding activated row line is precharged to the precharge potential again by a precharging operation. The control of this precharging operation, and also the activation of one of the row lines for the selection of one of the memory cells, is generally carried out through the use of a row access controller.
In particular in the case of synchronous memories, such as so-called SDRAM (Synchronous Dynamic Random Access Memory) or SGRAM (Synchronous Graphics Random Access Memory), the data processing speed is being progressively increased as a result of increasing requirements arising from raising the operating frequency (clock rate). As a result, the access time for an individual memory cell access is increasingly being shortened. At the same time, it is still necessary to ensure that a defined minimum time interval, in which a row line has to be activated in order to read or write a data signal, is maintained. This minimum time interval is generally physically necessitated, for example as a result of the length of the row line and the capacitive load connected thereto.
A precharging operation is normally initiated by applying a so-called precharge command, which, for example, is applied before or during a row access. In this case, it is basically possible for this precharge command to lead to a premature precharge, that is to say the relevant row line is precharged before the minimum time intervals has elapsed. If this minimum activation time interval of one of the row lines is violated, this can lead to a data loss during the reading or writing of a data signal.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory configuration which overcomes the above-mentioned disadvantages of the heretofore-known memory configurations of this general type and in which it is ensured that a minimum activation time interval of a row line is maintained during the reading or writing of a data signal, irrespective of when a row line is activated and/or how long a read operation or write operation lasts.
In addition, it is an object of the invention to provide a method of operating an integrated memory that ensures that the minimum activation time interval of a row line is maintained during the reading or writing of a data signal.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory configuration, including:
an integrated memory having a memory cell array with memory cells, column lines, and row lines;
the memory cells being connected to respective ones of the row lines for selecting one of the memory cells and being connected to respective ones of the column lines for one of reading and writing a data signal;
a row access controller operatively connected to the memory cell array, the row access controller activating one of the row lines for selecting one of the memory cells, and the row access controller controlling a precharging operation for precharging one of the row lines;
a control unit having a first input, a second input, a third input, and an output;
a first terminal for providing a decoded precharge command initiating a triggering of a precharging operation of one of the row lines, the first terminal being connected the first input of the control unit;
a second terminal for providing a signal indicating that a read operation or a write operation for a data signal has been finished, the second terminal being connected the second input of the control unit;
a third terminal for providing a signal containing information about a time interval during which an activated one of the row lines is activated, the third terminal being connected to the third input of the control unit; and
the output of the control unit being connected to the row access controller and outputting an output signal for triggering a precharging operation of one of the row lines.
In other words, the object of the invention is achieved by an integrated memory of the type described above having a control unit including a first input, which is connected to a signal terminal for a decoded precharge command, which initiates the triggering of the precharging operation of one of the row lines; a second input, which is connected to a signal terminal for a signal which indicates that the reading or writing of a data signal has been finished; a third input, which is connected to a signal terminal for a signal which contains information about a time interval during which an activated row line is activated; and an output which is connected to the row access controller in order to output an output signal to trigger the precharging operation of one of the row lines.
According to another feature of the invention, a central control device is connected to the first input and the second input of the control unit for controlling a memory cell access.
According to yet another feature of the invention, the row access controller is connected to the third input of the control unit.
According to another feature of the invention, a fourth terminal provides an address signal for addressing one of the row lines, and the control unit is connected to the fourth terminal and includes a storage circuit for storing address signals of row lines to be selected.
According to a further feature of the invention, the storage circuit includes a shift register. The shift register serially reads, in response to a respective precharge command, address signals of given ones of the row lines to be selected in a given sequence, the shift register outputs the address signals of the given ones of the row lines to be selected in the given sequence, and the control unit triggers, with the output signal from the output of the control unit, a precharging operation of one of the row lines in accordance with the address signals output by the shift register.
According to another feature of the invention, the integrated memory is a synchronous memory having a clock terminal for receiving a clock signal.
According to another feature of the invention, a synchronization circuit is connected upstream of the third input of the control unit for time-synchronizing the signal containing the information about the time interval with the clock signal.
With the objects of the invention in view there is also provided, a method of operating an integrated memory, the method includes the steps of:
providing an integrated memory having a memory cell array with memory cells, column lines, and row lines, the memory cells being connected to respective ones of the row lines for selecting one of the memory cells and being connected to respective ones of the column lines for reading or writing a data signal;
provi
Dietrich Stefan
Schöniger Sabine
Schrögmeier Peter
Weis Christian
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Greory L.
Phan Trong
Stemer Werner H.
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