Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2000-09-14
2001-11-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S145000, C365S201000
Reexamination Certificate
active
06314018
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated memory having memory cells, which are arranged within a cell array along bit lines, word lines and at least two plate segments and each have a selection transistor and a storage capacitor, one electrode of each storage capacitor being connected via the associated selection transistor to one of the bit lines and another electrode being connected to one of the plate segments, and a control terminal of each selection transistor being connected to one of the word lines.
An integrated memory of this type in the form of an FRAM (Ferro-Electric Random Access Memory) is described in U.S. Pat. No. 5,373,463, which shows a first variant of an FRAM in which the plate segments are arranged parallel to the word lines, each plate segment being assigned to a word line. Another variant is shown, furthermore, in which plate segments run parallel to the bit lines, each plate segment being assigned to a bit line. The memories described in U.S. Pat. No. 5,373,463 operate according to the so-called “Pulsed plate concept”. When information items are being written to or read from the memory cells, one of the word lines is activated, so that the associated selection transistors are switched on, and then the plate segment assigned to that memory cell which is intended to be accessed is brought firstly to a high supply potential and then to a low supply potential of the memory, that is to say is pulsed. Each access to one of the memory cells is thus connected with pulsing of the associated plate segment.
In ferroelectric memory cells, whose storage capacitors have a ferroelectric dielectric, aging phenomena such as the socalled “imprint” or the so-called “fatigue” occur and can lead to functional disturbances of the memory. Therefore, it is important, in the context of a memory test, to check whether the memory cells satisfy at least certain minimum requirements imposed on their resistance to aging. In order to check the aging effects, it is possible to carry out a large number of write and/or read accesses to each memory cell. Finally, the functionality of each cell is checked, so that it can be ascertained whether first defects rendering use of the memory impossible have already occurred on account of premature aging. Since today's memories have a multiplicity of memory cells, the above-described testing of the memory cells is very time-consuming.
SUMMARY OF THE INVENTION
The invention is based on the object, therefore, of specifying an integrated memory of the type mentioned in which it is possible to test the memory cells by carrying out a multiplicity of memory accesses with a reduction in the time needed.
This object is achieved by means of an integrated memory in accordance with patent claim
1
. The dependent claims relate to advantageous designs and developments of the invention.
The memory cells of the memory according to the invention are each connected to one of at least two plate segments. In a normal operating mode of the memory, accesses are made to the memory cells by the potential of only one of the plate segments in each case being pulsed. In a test operating mode, by contrast, the potentials of both plate segments are pulsed simultaneously.
The invention is based in the insight that although accesses have to be carried out exactly to individual memory cells during normal operation of a memory, this is not necessary for artificial aging of the memory cells in a test operating mode. Rather, access can be made to a larger number of memory cells in the test operating mode than in the normal operating mode. According to the invention, this is done by pulsing a different number of plate segments in the two operating modes.
According to one development of the invention, the potentials of the two plate segments are pulsed simultaneously in each case in the opposite direction in the test operating mode. This means that the plate segments assume complementary levels, which may be supply potential levels of the memory, for example, in the test operating mode. What this achieves is that effects which occur on account of capacitive couplings between the plate segments and the bit lines, on the one hand, and between the plate segments and the word lines, on the other hand, mutually compensate one another at least in part. This compensation is greater, the nearer the two plate segments are arranged to one another. Therefore, it is particularly advantageous if the plate segments are arranged directly adjacent to one another.
According to a further development of the invention, the potentials of the two plate segments are pulsed, in the test operating mode, in each case by two successive pulses with opposite levels in each case, and the memory has a short-circuiting element, which connects the two plate segments to one another and is temporarily switched on prior to the second pulsing of the plate potentials.
What this achieves is that prior to the pulsing of the two plate segments to opposite levels in each case, charge balancing is effected via the conductive short-circuiting element, so that less power is needed to achieve the level that is subsequently to be pulsed than in the case without short-circuiting.
According to one embodiment of the invention, the plate segments run parallel to the word lines and, in the test operating mode, for each plate segment, at least one of the associated word lines is activated during the pulsing of the plate potentials.
This means that during the pulsing of the plate potentials for the two plate segments, opposing charge transfers occur on those bit lines which are assigned to memory cells which are accessed in each case. These opposing charge transfers or currents having an opposite sign result from the opposite potential pulses of the two plate segments. Through the activation of a respective word line for each plate segment, memory cells both of one and of the other plate segment are connected to the same bit line via their selection transistors. Whereas, by way of example, a positive current flows onto the bit lines on account of a positive pulse on one plate segment, the negative pulse on the other plate segment effects a corresponding negative pulse on the same bit line. The two currents having an opposite sign compensate one another at least in part on the bit line. Through the compensation of the simultaneously flowing positive and negative charges, no large electrical charges have to be carried away by the bit lines. Corresponding lines which can carry large currents are not necessary, therefore, in the case of the invention. Particularly if the two simultaneously pulsed plate segments are arranged adjacent to one another, local balancing or compensation currents flow only in partial regions of the affected bit lines. This avoids relatively large parasitic voltage drops along the bit lines.
According to another embodiment of the invention, the plate segments are arranged parallel to the bit lines and, in the test operating mode, for each plate segment, at least one of the associated word lines is activated. Moreover, the memory has a potential line for a fixed potential and also at least two short-circuiting elements, via which one of the bit lines assigned to each plate segment is respectively connected to the potential line and which are both in the on state in the test operating mode during the pulsing of the plate potentials.
Since the plate segments run parallel to the bit lines in this embodiment, the simultaneous pulsing of both plate segments does not concern the same bit line. Therefore, the short-circuiting elements and the potential lines are necessary in order to achieve the charge compensation—described further above—during the opposite pulsing of the plate segments. In this embodiment, then, the charge compensation takes place between two bit lines which are assigned to different plate segments. Otherwise, the statements regarding the embodiment explained above apply to this embodiment of the invention.
In both embodiments of the invention expla
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Tan T.
Stemer Werner H.
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