Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2000-04-28
2001-07-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
Reexamination Certificate
active
06259641
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory having sense amplifiers disposed on opposite sides of a cell array.
The article, The Charge-Share Modified (CSM) Precharge-Level Architecture for High-Speed and Low-Power Ferroelectric Memory, H. Fujisawa et al., in IEEE Journal of Solid-State Circuits, Vol. 32, No 5, May 1997, page 655 ff. describes a ferroelectric memory (FeRAM or RAM) whose memory cells are of the one-transistor/one-capacitor type. The storage capacitor has a ferroelectric dielectric. The memory cells are disposed at points of intersection of bit lines and word lines. The bit lines are connected to a common sense amplifier through n-channel transistors. In addition, each bit line is connected through a p-channel transistor to a plate potential, to which the electrode of each storage capacitor remote from the selection transistor is also connected. The control connection of the n-channel transistor and of the p-channel transistor in each bit line is connected to a column selection line. Only one of the bit lines is ever accessed at the same time using the column selection lines, the bit line then being conductively connected to the sense amplifier through its n-channel transistor. The other column selection lines remain at a low level, so that the associated bit lines are conductively connected to the plate potential. Although, when one of the word lines is activated, one of the selection transistors in the memory cells on each bit line is turned on, the state stored in the storage capacitors in the unselected bit lines is not affected because the p-channel transistors cause the plate potential to be present on both electrodes of the capacitors. A voltage drop of 0 V across a ferroelectric storage capacitor does not change the polarity of the capacitor. The polarity affects the capacitance of the storage capacitor and corresponds to a particular stored logic state.
In integrated memories, the memory cells disposed at points of intersection of adjacent bit lines and word lines form cohesive cell arrays. If each bit line has to have an appropriate sense amplifier allocated to it, it is beneficial to dispose the sense amplifiers not only on one side of the cell array but alternately on opposite sides of the cell array. Then, there is more space available for configuring the components of the sense amplifiers.
In integrated memories, a plurality of adjacent bit lines is often combined to form a common column having an associated column selection signal. If one of the column selection lines is activated, sense amplifiers on both sides of the cell array are then connected to the bit lines in the appropriate columns and, during read access, amplify the signals read from the addressed memory cells onto these bit lines. To ensure that the surface requirement for the column selection lines in the cell array does not become too large, the column selection lines must be limited in number. On the other hand, limiting the number of column selection lines means that each column selection line has a relatively large number of associated bit lines. Accordingly, during any memory access, a large number of sense amplifiers need to be activated at the same time. Activating more sense amplifiers at the same time increases the power consumption of the integrated memory. In memory cells whose content is destroyed during read access, the sense amplifier is used for writing back the data that has just been read out. Consequently, all the sense amplifiers connected to selected bit lines must be activated normally. Such is the case for DRAMs and FRAMs.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory having sense amplifiers disposed on opposite sides of a cell array that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that reduces the power consumption compared to conventional solutions for the same ratio of the number of column selection lines to the number of bit lines, that is to say, when the surface requirement of the column selection lines in the cell array is constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, an integrated memory, including at least one cell array having bit lines including first and second bit lines, word lines, and memory cells disposed at points of intersection of the first and second bit lines with the word lines in the at least one cell array, the memory cells each having a memory content, and, when one of the memory cells is addressed, the memory content of the memory cells is not affected provided respective bit lines of the bit lines associated with each of the memory cells are at a standby potential, sense amplifiers disposed on opposite sides of the at least one cell array for amplifying data read from the memory cells onto the bit lines, the sense amplifiers each associated with respective ones of the first and second bit lines, first switching elements having first control connections, the first switching elements connecting each of the bit lines to a respectively associated one of the sense amplifiers, the first switching elements being on when a first logic state appears at the first control connections, second switching elements having second control connections, the second switching elements connecting each of the bit lines to the standby potential on a side of a respective one of the first switching elements remote from an associated sense amplifier, the second switching elements being on when a second logic state appears at the second control connections, column selection lines each connected to the first control connections and the second control connections in at least one of the first bit lines and at least one of the second bit lines, third switching elements connecting each of the bit lines to the standby potential, the third switching elements each having a control input, a first control line connected to the control input of each of the third switching elements in the first bit lines , and a second control line connected to the control input of each of the third switching elements in the second bit lines.
The memory according to the invention has first switching elements, through which each bit line is connected to the associated sense amplifier, and second switching elements, through which each bit line is connected to a standby potential. The first and second switching elements in each bit line are connected to a column selection line. In addition to the first and second switching elements, the memory has third switching elements, through which each bit line is likewise connected to the standby potential. A first control line is connected to a respective control input of all the third switching elements in the first bit lines, which are associated with sense amplifiers on a first side of the cell array. A second control line is connected to a respective control input of all the third switching elements in the second bit lines, which are associated with sense amplifiers on a second side of the cell array.
Thus, in the memory according to the invention, the bit lines are selected not only through the column selection lines, but also through the first and the second control line. Advantageously, during operation of the memory, only one of the two control lines can be brought to a potential that disables the associated third switching elements. Then, although all the bit lines in a column selected through the column selection line are conductively connected to the associated sense amplifier through the first switching elements, those bit lines whose third switching elements are turned on through the appropriate control line are still at the standby potential. Thus, the two control lines can be used to select whether the first or the second bit lines in a selected column are to be accessed during memory access. Accordingly, only half of the sense amplifiers associated with the bit lines in a column need then be activated at th
Bohm Thomas
Manyoki Zoltan
Rohr Thomas
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Phung Anh
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