Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-09-14
2001-10-30
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S145000, C365S201000
Reexamination Certificate
active
06310812
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated memory having memory cells, arranged at crossover points of word lines and bit lines, and reference cells, arranged at crossover points of a reference word line and the bit lines and serve for generating a reference potential on the bit lines prior to a readout of the memory cells.
Such an integrated memory in the form of a ferroelectric memory or FRAM (Ferroelectric Random Access Memory) is described in U.S. Pat. No. 5,844,832. Prior to a read access to the memory cells, a specific potential is written to the reference cells and the latter are subsequently read out onto the bit lines. Afterwards, in each case two adjacent bit lines onto which reference cells having different levels were read out are short-circuited with one another, so that a reference potential corresponding to the average value of the two different levels is established on these two bit lines. The reference cells are thereby constructed identically to the regular memory cells. Prior to each readout of the memory cells, that is to say, for example, also during a test of the memory cells, the reference potential is generated on the bit lines by means of the reference cells in the manner described in order to feed the defined reference potential to sense amplifiers, which are connected to the bit lines, prior to an evaluation of the bit line potentials which is to be carried out by the sense amplifiers.
Errors during the readout of one of the memory cells in the prior art memory can have two different causes. On the one hand, the memory cell that is currently to be read out or the word line connected to it may have a defect. On the other hand, the associated reference cell may have a defect, so that the reference potential is not generated correctly, thereby preventing error-free evaluation of the bit line potential by the sense amplifiers. It is desirable, therefore, to be able to ascertain whether or not an error occurring during the readout of one of the memory cells is caused by a malfunction of the reference cells.
SUMMARY OF THE INVENTION
The object of the invention is to provide an integrated memory with memory cells and reference cells which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which allows the testing of the functionality of the reference cells in a simple manner.
With the above and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
word lines and bit lines and a plurality of memory cells arranged at respective crossover points of the word lines and the bit lines;
first reference cells arranged at crossover points of at least one first reference word line and the bit lines, the first reference cells, in a normal operating mode, generating a reference potential on the bit lines prior to a readout of the memory cells;
second reference cells arranged at crossover points of at least one second reference word line and the bit lines, the second reference cells, in a test operating mode, generating a reference potential on the bit lines prior to a readout of the first reference cells.
In other words, the novel memory has memory cells, which are arranged at crossover points of word lines and bit lines, and first reference cells, which are arranged at crossover points of at least one first reference word line and the bit lines and, in a normal operating mode, serve for generating a reference potential on the bit lines prior to a readout of the memory cells. In addition, the device has second reference cells, which are arranged at crossover points of at least one second reference word line and the bit lines and, in a test operating mode, serve for generating a reference potential on the bit lines prior to a readout of the first reference cells.
The second reference cells thus enable functional checking of the first reference cells in the test operating mode, in that, with their aid, a corresponding reference potential is generated on the bit lines. Consequently, the first reference cells can be read out in the test operating mode in the same way as this is done with the normal memory cells in the normal operating mode. If a defect in the second reference cells can be ruled out, the conclusion that can be drawn if a functional disturbance occurs during the readout of one of the first reference cells is that there is a defect in the first reference cell. If, by contrast, it is not known whether the second reference cells are intact, and if an error is detected during the readout of one of the first reference cells in the test operating mode, it is certain that either the corresponding first reference cell or the second reference cells used for generating the reference potential has or have a defect.
In accordance with an added feature of the invention, the second reference word line is identical to one of the word lines and the second reference cells are identical to the memory cells connected to the word line. This means that, in the normal operating mode, the first reference cells serve for generating the reference potential prior to a readout of one of the normal memory cells, while in the test operating mode, the normal memory cells of the second reference word line serve for generating the reference potential prior to a readout of one of the first reference cells. In this development, no further cells are necessary in addition to the normal memory cells and first reference cells, so that a memory of this type can be realized with a comparatively small area.
In accordance with an additional feature of the invention, the memory device further comprises:
address inputs for feeding in row addresses for addressing the word lines;
a row decoder configured to:
enable addressing the second reference word line by means of a specific one of the row addresses in the normal operating mode; and
enable addressing the first reference word line by means of a specific row address in the test operating mode.
This enables the first reference word line to be addressed in the test operating mode in the same way as an arbitrary one of the word lines is addressed in the normal operating mode.
In accordance with a concomitant feature of the invention, the memory device further comprises:
a plurality of second reference word lines;
a control input for receiving a control signal, for effecting a selection of at least one of the second reference word lines, and wherein the second reference cells subsequently serve for generating the reference potential on the bit lines in the test operating mode prior to a readout of the first reference cells.
The control signal is used to effect selection of at least one of the second reference word lines, whose second reference cells subsequently serve for generating the reference potential on the bit lines in the test operating mode prior to a readout of the first reference cells. In this development, in the test operating mode one of the first reference cells can be read out multiply, during which the necessary reference potential is generated on the bit lines successively in each case by different second reference cells. It can therefore be ascertained whether the occurrence of a defect during the readout is to be attributed to a malfunction of the corresponding first reference cell or of the second reference cell. Specifically, if the first reference cell is defective, when it is read out an incorrect result will always be produced, irrespective of the second reference cell used in each case. By contrast, it is improbable that a plurality of second reference cells, assigned to different second reference word lines, will be defective simultaneously.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory having memory cells and reference cells, it is neverth
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Tan T.
Stemer Werner H.
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