Integrated memory having improved testing means

Details Integrated memory having improved testing means Integrated memory having improved testing means

1993-02-05

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

36518907, 36518909, 365210, G11C 700

Patent

active

053553411

ABSTRACT:
An electrically-programmable integrated circuit memory in which the selected memory cell is read by comparing its current output with that of a reference cell, plus a bias current. The bias current is different in test mode than it would be during a normal read operation. The result of this is that, in test mode, cells whose current output is marginal in the unprogrammed state will be detected as faulty, even though those same cells would correctly be read as unprogrammed.

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patent: 5091888 (1992-02-01), Akaogi
patent: 5117394 (1992-05-01), Amin et al.
patent: 5142495 (1992-08-01), Canepa
patent: 5218570 (1993-06-01), Pascucci et al.
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, New York, pp. 1150-1156 R. Gastaldi, "A 1-Mbit CMOS EPROM with enhanced verification".
Patent Abstracts of Japan, vol. 13, No. 125 (P-847) Mar. 28, 1989.

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