Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2002-12-18
2004-04-20
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189090
Reexamination Certificate
active
06724672
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated memory having a memory cell array, word lines for selecting memory cells, bit lines for reading out or writing data signals of the memory cells, and a precharge circuit for precharging at least one of the bit lines.
An integrated memory generally has a memory cell array including word lines and bit lines. The memory cells are arranged at crossover points between the word lines and the bit lines. The memory cells are connected to one of the bit lines for reading out or writing in a data signal, in each case via a selection transistor whose control input is connected to one of the word lines. A word line selects selection transistors of corresponding memory cells along the word line and opens the selection transistors. If the respective selection transistor is open, then the charge stored in the cell capacitor can pass onto the corresponding bit line, and from there into a read/write amplifier.
In integrated memories, generally after the writing or reading of data signals, the corresponding bit line is precharged to a positive supply voltage of the memory (also referred to as voltage VDD). This precharge voltage is chosen since, on the one hand, it can be made available comparatively simply, and on the other hand, it entails a high so-called static stability for data access. The static stability (so-called static noise margin SNM) is a characteristic quantity for the security during the read-out of data signals and is of great importance for the reliability of the read-out operation. The static stability itself depends on the magnitude of the precharge voltage. A maximum of the static stability is achieved for a precharge voltage VDD at the level of the positive supply voltage of the memory.
The level of the supply voltage of memories is constantly reduced primarily in view of increasing requirements with respect to reliability and low energy consumption. On the other hand, the increase in memory size demands higher processing speeds of memories. By way of example, in the case of large project-specific low-power memories, a large part of the power taken up can be reduced by no longer precharging the bit lines to the positive supply voltage VDD of the memory, but rather only to a precharge voltage that is lower in comparison therewith. A theoretical consideration for precharging a bit line to a voltage less than the positive supply voltage VDD of the memory and an associated reduction of the static stability is discussed in more detail in Th. Nirschl, B. Wicht, D. Schmitt-Landsiedel: High Speed, Low Power Design Rules for SRAM Precharge and Self-timing under Technology Variations; and In: Power and Timing Modeling, Optimization and Simulation 2001, Proceedings of the 11th Intern. Workshop, Yverdon-les-Bains, Switzerland, September 2001, pp. 7.3.1-7.3.10.
In order to provide a precharge voltage that is less than the positive supply voltage VDD, reference voltage sources that generate a constant voltage as the precharge voltage are generally used. Simple reference voltage sources can be constructed for example using voltage dividers with a corresponding number of resistors. However, reference voltage sources constructed in this way generally have the disadvantage of a relatively high power loss. A reference voltage for so-called high-end applications can also be generated by a bandgap reference. The bandgap reference can also be used to satisfy comparatively stringent stability requirements made of a precharge voltage, but a circuit of this type has a comparatively high area consumption.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory of the type mentioned in the introduction which overcomes the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, an object of the invention is to provide an integrated memory of the type mentioned in the introduction, which enables the power loss of the memory to be reduced in conjunction with comparatively low area consumption.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory with a memory cell array including a plurality of memory cells, a plurality of word lines for selecting the plurality of the memory cells and a plurality of bit lines for reading out or writing data signals of the plurality of the memory cells. A precharge circuit is connected to at least one of the plurality of the bit lines. The precharge circuit is for precharging the one of the plurality of the bit lines to a precharge voltage generated from a supply voltage that is different from the precharge voltage. The precharge circuit has a loop regulating circuit for setting the precharge voltage using an actual voltage of the one of the plurality bit lines.
In accordance with an added feature of the invention, the precharge circuit has a regulator exhibiting hysteresis.
In accordance with an additional feature of the invention, the precharge circuit has a Schmitt trigger.
In accordance with another feature of the invention, there is provided, a terminal for obtaining a supply voltage. The precharge circuit includes a precharge transistor having a controlled path connected to the terminal for obtaining the supply voltage. The precharge transistor is turned on or off depending on an actual voltage of the one of the plurality of the bit lines.
In accordance with a further feature of the invention, the precharge transistor is of a p conductivity type or an n conductivity type.
In accordance with a further added feature of the invention, there is provided, a plurality of precharge circuits and a plurality of switches. The plurality of the bit lines are organized into a plurality of bit line pairs. Each one of the plurality of precharge circuits is provided for a respective one of the plurality of the bit line pairs. Each one of the plurality of the switches is for connecting together respective ones of the plurality of the bit lines associated with a respective one of the plurality of the bit line pairs. The precharge circuit of the integrated memory serves for precharging at least one of the bit lines to a precharge voltage. The precharge voltage is generated from a supply voltage of the memory, which differs from the precharge voltage. In particular, the magnitude of the precharge voltage is lower than that of the supply voltage of the memory, which, by way of example, is a positive supply voltage VDD of the memory. According to the invention, for setting the precharge voltage, the precharge circuit has a loop regulating circuit using an actual voltage of the corresponding bit line to be precharged. The precharge circuit can thus advantageously be realized by a local loop regulation requiring only a comparatively simple circuit which takes up only relatively little area. Integration into an existing memory design is possible with little outlay. Moreover, using a local loop regulation, it is possible for the power consumption or the power loss of the precharge circuit to be kept low since the precharging can be controlled in a targeted manner depending on the actual voltage of the bit line being precharged. For the case where the actual voltage reaches the predetermined value of the precharge voltage, the precharging of the relevant bit line can be interrupted or ended. In this case, the precharge circuit takes up essentially no power, as a result of which the power loss of the memory can be reduced overall.
In an advantageous embodiment of the inventive memory, the precharge circuit has a regulator exhibiting hysteresis. This advantageously makes it possible to avoid the situation in which driven actuators or control circuits of the loop regulating circuit are actuated correspondingly often on account of harmonics or superimposed interference. In a preferred embodiment of the invention, the precharge circuit has a switching amplifier with hysteresis in the form of a Schmitt trigger.
In an advantageous development of the inve
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Mai Son
Stemer Werner H.
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