Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-12-13
2003-07-15
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S205000, C365S149000
Reexamination Certificate
active
06594188
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to an integrated memory having a cell array with addressable column lines and addressable row lines and a charge equalization device. The invention furthermore relates to a method for writing a datum to a memory cell of the integrated memory having the addressable column lines, the addressable row lines, amplifier circuits and the charge equalization device.
In dynamic memory modules of conventional configurations, write access and read access to the memory differ inter alia in terms of the point in time at which writing and reading data are in each case present on the (external) data lines. In the case of writing, the data are provided on the column lines essentially simultaneously with the write command and the address to which writing is to be effected. In the case of reading, in contrast, a certain time (read latency) is required in order, after the read command, to localize the data in the memory (address decoding), to read out the stored charge, to amplify the signal and to transport it to the data lines. Therefore, when a changeover is made between writing and reading, gaps arise in the data stream to/from the memory, in which gaps no data are present on the data lines.
The gaps in the data stream are usually avoided to the greatest possible extent by artificially delaying the application of the writing data to the data line (write latency). This is carried out in order e.g. still to be able to read data of a previous read command on the data lines while a write command is already been sent. Thus, the write latency is also provided in addition to the read latency.
The write latency and the read latency are preferably approximately of the same length in order to ensure a continuous data stream from and to the memory. Since, during the read-out of the data, the data lines are enabled again only after the read latency time has elapsed, the data lines cannot be occupied with writing data until at this point in time. However, since the transporting of the writing data from the data lines to the memory cells and also the charge reversal of the column line entail a time delay, a gap arises in the data stream on the external data lines.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory having a cell array and charge equalization devices, and a method for the accelerated writing of a datum to the integrated memory that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for writing a datum to a memory cell of a memory cell array having addressable column lines, addressable row lines, amplifier circuits connected to the addressable column lines, and a charge equalization device for charge equalization of the addressable column lines. The method includes the steps of activating an addressed row line; switching-off an amplifier circuit on an addressed column line; equalizing a charge potential on the addressed column line using the charge equalization device; and switching-on the amplifier device for the addressed column line to write the datum to an addressed memory cell.
The invention is based on the fact that the writing of the datum to the dynamic memory cell via the column line proceeds more rapidly if the column line and the storage capacitance situated thereon are at a potential between the respective voltage potentials for the high state and the low state. This makes it possible to reduce the time for charge reversal of the relevant column line and of the relevant storage capacitance. Thus, e.g. a charge reversal from a high voltage potential to a low voltage potential, which corresponds e.g. to a change in the datum present on the column line from a high state to a low state, requires more time than a charge reversal of the column line from an intermediate medium voltage potential to a high or low voltage potential.
Since the longest charge reversal time which can occur during the write operation always determines the total writing time, the time delay in the case of writing is defined by a charge reversal of a data line from a high to a low state, or vice versa.
The potential lying between the high and low potentials is obtained with the aid of the charge equalization device which, in accordance with a control signal, short-circuits one of the column lines with a charge equalization element, so that the charges situated there are equalized. The charge equalization element used is preferably a further column line, particularly preferably an adjacent column line, which is not connected to the addressed row line via a memory cell.
The charge differences on the column lines arise because the charges situated on the adjacent column lines have been differentially expanded beforehand by a preamplifier circuit. In this case, the column line on which the memory cell to be read is situated is pulled to a potential which corresponds to the content of the memory cell, high charge level for a stored logic “1” or low charge level for a stored logic “0”. The column line adjacent thereto is pulled to another potential, which corresponds to the inverted content of the memory cell to be read. What is advantageously achieved by the equalization of the charge by the charge equalization devices immediately prior to a write operation is that less charge has to be subjected to charge reversal in the case of writing to a memory cell, and the time required for this is thereby reduced.
In the case of conventional memories, it has hitherto been customary to provide charge equalization devices between adjacent column lines, which are driven jointly if none of the row lines is addressed. This is necessary in order to pull the adjacent column lines to the same potential before a read operation in order that, during subsequent renewed reading, the small charge differences which arise as a result of the charge of a storage capacitor being switched onto the respective column line can be detected by the preamplifier circuit.
According to the invention, the charge equalization devices that are customary in conventional memories are controlled by a control device. During the write latency time, the memory cells that are to be written to are already addressed by the row lines. Activation of all the charge equalization devices would then result in that all the memory cells situated on the activated row lines would be erased without new contents subsequently being written to all the erased memory cells.
This is now avoided according to the invention in that the charge equalization devices are driven separately. In this way, only the storage capacitor and the column lines whose associated memory cell is intended to be written to are provided with an equalized potential.
Furthermore, it may advantageously be provided that, after a write operation, the row lines are deactivated and then all the charge equalization devices situated on the column lines are activated, so that the voltage potentials on all the column lines are equalized with their adjacent column lines in each case. In this way, the column lines are prepared for a subsequent read operation, and it is possible to avoid the situation in which the charge situated on the column lines conceals the charge to be read from the memory cells, so that the latter charge can no longer be reliably detected. The respectively adjacent column lines are connected to an amplifier circuit which amplifies the small charge differences which occur after a process of reading from a storage capacitor onto the column lines, so that the charge differences can be identified by a down stream logic unit.
In accordance with an added mode of the invention, there is the step of equalizing a charge potential on one of the column lines with a charge potential on another of the column lines.
In accordance with an additional mode of the invention, there is the step of carrying out the equalizing of the charge
Hoang Huan
Infineon - Technologies AG
LandOfFree
Integrated memory having a cell array and charge... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated memory having a cell array and charge..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory having a cell array and charge... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3009332