Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-10-01
2004-06-15
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189011, C365S191000, C365S193000, C365S189120
Reexamination Certificate
active
06751130
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to an integrated memory, to a method for operating such an integrated memory, and to a method for operating a memory system with a plurality of such integrated memories.
An integrated memory, particularly in the form of a DRAM memory (dynamic random access memory) generally has a memory cell array with word lines and bit lines, at whose crossover points memory cells are arranged. Via the word lines, memory cells to be read are selected and data of the selected memory cells are written to the memory cells or read from the memory cells via connected bit lines.
During the initialization of an SDRAM memory (synchronous DRAM), a so-called mode register set command is usually applied, by means of which a corresponding mode register is written to. The latter is used in order to define a specific operating mode of the SDRAM. By way of example, a burst length, a burst type, a so-called CAS latency and an operating mode of the memory are defined by means of the mode register (CAS, column access strobe, column address signal).
The CAS latency generally defines the number of clock cycles of a clock signal which is provided between the beginning of the read access and the beginning of data outputting to outside the memory. The CAS latency thus indicates the number of clock cycles after which the data are available after a read access on an external bus. This so-called read CAS latency is thus a value—relative to a clock signal—for a latency time between the beginning of the read access and the beginning of data outputting to outside the memory. During a read access, a data packet is obtained on the bus at a defined instant. In this case, the CAS latency is generally programmed and set depending on the operating frequency of the memory in order to obtain an optimum data throughput at every operating frequency during a read access to one of the memory cells.
In a standard SDRAM memory, the CAS latency can generally be programmed between values of two and three clock periods. This value is stored in the mode register. If the memory is operated at a comparatively low operating frequency, the CAS latency can assume both values. For the case where the operating frequency of the clock and thus of the memory is increased, the situation can occur wherein the memory no longer operates reliably with a CAS latency of two clock periods since, under certain circumstances, the data outputting to outside the memory begins before the data are present at the output driver. In this case, it is necessary to program the memory with a CAS latency of three clock periods. This programming is carried out in a system start, for example. In this case, errors may arise during the programming, so that there is the risk of the memory not operating in a manner free from errors in later operation.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables a comparatively accurate and error-free setting of a value for a CAS latency for a read-out operation of the memory. It is a further object of the present invention to specify a method for operating such a memory and a method of operating a memory system having a plurality of such memories.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
an output driver for outputting data;
a selection circuit connected to the output driver, the selection circuit having a control input for receiving a control signal for setting a selectable latency, relative to a clock signal, between a beginning of a read access and an outputting of the data to outside the memory, the selection circuit, depending on a selected latency, forwarding the data to be output to the output driver at different instants relative to the beginning of the read access;
a detection circuit for comparing the data to be output with desired data, the detection circuit having an output connected to the control input of the selection circuit for outputting an output signal for setting the selected latency depending on a comparison result.
In accordance with an added feature of the invention, the selection circuit has a first input connected to a first data path and a second input connected to a second data path, the first data path outputs the data to be output at a first instant and the second data path outputs the data to be output at a second instant following the first instant, and wherein the first and second inputs are enabled alternatively to one another by the selection circuit.
In accordance with an additional feature of the invention, clock-controlled multivibrators for receiving the data to be output are connected in the first and second data paths. The second data path has a higher number of the multivibrators than the first data path. Preferably, the detection circuit is connected to an input of one of the multivibrators.
In accordance with another feature of the invention, a register circuit stores a value of the latency. The register circuit is connected between the control input of the selection circuit and the output of the detection circuit. In a preferred embodiment, the register circuit has an output through which the value of the latency can be read out to the outside of the memory.
With the above and other objects in view there is also provided, in accordance with the invention, a memory processing method, which comprises:
providing an integrated memory as summarized above, and operating the memory by:
in a write mode, writing data to the memory to form stored data;
subsequently, in a read mode, reading out the stored data, and comparing the data being read out with desired data in the detection circuit; and
if the data being read out and the desired data do not correspond, increasing the latency with the detection circuit.
In accordance with a concomitant feature of the invention, the write mode and the read mode proceed in an initialization operating mode of the memory.
With the above and other objects in view there is also provided, in accordance with the invention, a method for operating a memory system, which comprises:
providing at least two of the above-summarized integrated memories;
operating each of the integrated memories in an initialization operating mode, by:
in a write mode, writing data to be stored to the respective memory;
afterward, for each memory, in a read mode, reading out the stored data and comparing the data being read out with desired data in the detection circuit of the respective memory;
if the data read out and the desired data do not correspond, increasing the latency by the detection circuit; and
if the latencies of the memories do not correspond to one another:
operating the memory having a smaller latency with an increased clock frequency in a further initialization operating mode and increasing the latency thereof; or
operating the memory system with different latencies.
In other words, the integrated memory according to the invention has a selection circuit having a control input for receiving a control signal, which serves for setting a selectable latency (CAS latency)—relative to a clock signal—between the beginning of a read access and the provision of the data to outside the memory. Depending on the selected latency, data to be output are forwarded to an output driver by the selection circuit at different instants relative to the beginning of the read access. A detection circuit serves for comparing the data to be output with desired data and has an output for outputting an output signal, by means of which the latency can be set depending on the comparison result. The control input of the selection circuit is coupled to the output of the detection circuit.
The integrated memory according to the invention makes it possible to set an optimum value for the CAS latency on-chip in a self-adjusting manner. This enables a comparat
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Nguyen Viet Q.
Stemer Werner H.
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