Integrated memory circuits

Details Integrated memory circuits Integrated memory circuits

1982-09-30

1984-06-05

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365210, G11C 700, G11C 800

Patent

active

044532350

ABSTRACT:
This is an improved approach to the operation of an integrated circuit memory, especially of the MOS type. The approach is especially suitable for use with CMOS read-only memories (ROMs). Specific improvements include address-triggered pulse generation, power switching and sharing for individual cells, a pseudo-dynamic approach to achieve quasi-static operation, self-compensating means for both "word" lines and "bit" lines, use of complementary decoding devices for the mutually orthogonal directions in the memory, and an improved output function. Specific circuitry for implementing the above approaches in a CMOS integrated circuit includes an address-triggered pulse generator, a self-tracking reference voltage source derived from both the "word" lines and the "bit" lines, an output stage with a CMOS driver into a bipolar transistor, and a sense amplifier including a capacitor.

REFERENCES:
patent: 4037217 (1977-07-01), Savarese
patent: 4094008 (1978-06-01), Lockwood et al.
Balasubramanian et al., "Two Device Per Bit, Precharged ROS with Differential Sensing," IBM Tech. Disc. Bul., vol. 19, No. 1, 6/76, pp. 164-165.

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