Integrated memory circuit with parallel and serial input and out

Details Integrated memory circuit with parallel and serial input and out Integrated memory circuit with parallel and serial input and out

1989-08-25

1991-05-07

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, 36518912, 365154, 365219, 307445, 307585, 377 69, 377 75, 377 77, G11C 706

Patent

active

050142445

ABSTRACT:
An integrated memory circuit in which memory cells are arranged in rows and columns, each column having a separate sense amplifier. The memory columns can be coupled to neighboring memory columns by additional transistors and the gain of the sense amplifiers in the even and the odd columns is adjustable. Consequently, information can also be serially shifted from one column to another, so that the information can be written and read not only in parallel but also serially.

REFERENCES:
patent: 4445201 (1984-04-01), Pricer
patent: 4646270 (1987-02-01), Voss
patent: 4710649 (1987-12-01), Lewis
patent: 4723228 (1988-02-01), Shah et al.
patent: 4769789 (1988-09-01), Noguchi et al.
patent: 4773045 (1988-09-01), Ogawa
patent: 4795557 (1988-05-01), Ogawa et al.
patent: 4839868 (1989-06-01), Sato et al.
patent: 4897816 (1990-01-01), Kogan

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