Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-04-17
1989-04-18
Hecker, Stuart N.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365190, 365203, 365 51, G11C 700
Patent
active
048233196
ABSTRACT:
In a memory cell which is connected between two bit lines, information is stored after selection by causing a first bit line to convey a signal which is complementary to that on a second bit line. It is known, starting from a single data supply line which may convey either a high or a low signal, to provide a memory circuit per column with inverting means so as to be able to charge both bit lines complementarily. Here, this complementary charging is done by connecting, upon selection, the first bit line to the data supply line and connecting a transistor with its main electrodes between ground and the second bit line, which transistor receives the data at its control electrode. This transistor then constitutes, with the bit line load, an inverter. Lay-out aspects relate to the common use of substrate area of two adjacent columns and the common use of a contact in the shown circuit arrangement.
REFERENCES:
patent: 3848236 (1974-11-01), Troutman
patent: 3949382 (1976-04-01), Yasui
patent: 4133611 (1979-01-01), Baker
patent: 4287571 (1981-09-01), Chakravarti et al.
patent: 4715014 (1987-12-01), Tuvell et al.
Biren Steven R.
Garcia Alfonso
Hecker Stuart N.
U.S. Philips Corporation
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