Integrated memory and method for testing an integrated memory

Details Integrated memory and method for testing an integrated memory Integrated memory and method for testing an integrated memory

2007-06-26

2007-06-26

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Data formatting to improve error detection correction...

C714S719000, C365S201000

Reexamination Certificate

active

10726990

ABSTRACT:
An integrated memory and method for testing an integrated memory is provided herein. In order to test an integrated memory having a main data memory with a plurality of data memory units, a data memory unit is addressed and input test data for testing the addressed data memory unit are applied to the main data memory. The output test data are read out from the main data memory and compared with expected desired output test data in a self-test unit. Deviations detected during the comparison are buffer-stored in a redundancy analysis memory. These information items buffer-stored in the redundancy analysis memory are read out and transferred to a computing unit. In the computing unit, the defect positions in the output test data are identified, and a repair strategy is determined by means of redundant rows and/or redundant columns and/or redundant words provided. The redundant words required for the repair strategy are written to the redundancy analysis memory and activated.

REFERENCES:
patent: 5506807 (1996-04-01), Ferrant et al.
patent: 5588115 (1996-12-01), Augarten
patent: 6469932 (2002-10-01), Roohparvar et al.
patent: 6560149 (2003-05-01), Muller
patent: 6590816 (2003-07-01), Perner
patent: 6731550 (2004-05-01), McClure
patent: 2002/0157049 (2002-10-01), Kaiser et al.
patent: 39 24 695 (1990-02-01), None
patent: 100 02 127 (2001-08-01), None
patent: 101 09 335 (2002-09-01), None
patent: 101 10 469 (2002-09-01), None
patent: 101 19 144 (2002-10-01), None
patent: 0702373 (1996-03-01), None
“Increased Throughput for the Testing and Repair of RAM's with Redundancy”, Ramsey W. Haddad, Anton T. Dahbura and Anup B. Sharma, EIII Transactions on Computers, vol. 40, No. 2, Feb. 1991, pp. 154-166.

Affiliated with

Also associated with

Rating

Integrated memory and method for testing an integrated memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated memory and method for testing an integrated memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated memory and method for testing an integrated memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3835409