Integrated gate bipolar transistor and method of...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S700000

Reexamination Certificate

active

06482701

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon Japanese Patent Application No. Hei. 11-221242 filed on Aug. 4, 1999, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to method of manufacturing a semiconductor device, and particular to a method of manufacturing a semiconductor device having a trench formed in a semiconductor substrate. This invention also related to insulated gate bipolar transistors (IGBT), and to a method of manufacturing an insulated gate bipolar transistor.
2. Related Art
In a hybrid car or an electric vehicle (EV), an inverter module is used as a converter that converts a large direct current from a battery into an alternating current for an actuating system such as a motor. For example, IGBT elements are used as the inverter module.
Here, recently, a trench gate type IGBT element, having a trench gate structure as a device structure, has been proposed to downsize the IGBT element or lower a resistance of the IGBT. According to this kind of trench gate type IGBT element, a trench (deep groove) is formed in a silicon substrate by using a dry etching (anisotropic etching); and a gate is formed on the trench.
In a case of the trench gate type IGBT element in the above, a corner of a bottom portion of the trench is angular. Therefore, a film quality of a gate oxide film may deteriorate or may be thinned at this corner, or an electric field may concentrate at this corner. As a result, a withstand voltage breakdown may easily occur at this corner.
Incidentally, the inconvenient in the above may be cancelled by rounding off the corner at the bottom of the trench. Conventionally, the corner at the bottom of the trench has rounded off by using a method as described in JP A 64-57623 or JP A 9-330928. According to the method in these Japanese patent applications, after forming the trench using an anisotropic etching, the corner is rounded off by conducting an isotropic etching to the bottom of the trench.
However, such the isotropic etching is conducted to sufficiently round off the corner, since silicon is excessively etched, a structure of the trench or a structure of a device may be changed from a designed structure. Therefore, it needs to reduce an amount of etching using the isotropic etching as much as possible. As a result, the corner at the bottom of the trench is not sufficiently rounded off, so that a radius of curvature of the corner may become small.
SUMMARY OF THE INVENTION
This invention has been conceived in view of the background thus far described and its first object is to sufficiently round off a corner at a bottom of a trench with restricting silicon from being excessively etched.
According to the present invention, a trench having a bottom is formed at a surface of a semiconductor substrate by conducting an anisotropic etching. After forming the trench, a bottom of the trench including a corner portion is processed into a concave shape by conducting a concave etching. Here, the concave etching etches the semiconductor substrate so that a diameter of the trench is gradually reduced as the etching advances. After processing the corner portion, the corner portion of the bottom of the trench is rounded off by conducting an isotropic etching. Since the corner portion is chamfered by using the concave etching, a radius of curvature of the corner portion at the bottom of the trench can be increased even if an amount of the etching using the isotropic etching conducted later is small.
In other words, according to the present invention, the radius of curvature r
1
of the bottom of the trench can be freely and easily controlled, by controlling a depth and a sidewall angle by the concave etching and by controlling the amount of etching using the isotropic etching. Therefore, even if the amount of the etching using the isotropic etching e
1
is set small, the corner portion of the bottom of the trench can be efficiently rounded off, and excessive etching of the silicon can be prevented.


REFERENCES:
patent: 4693781 (1987-09-01), Leung et al.
patent: 4839306 (1989-06-01), Wakamatsu
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5236861 (1993-08-01), Otsu
patent: 5242845 (1993-09-01), Baba et al.
patent: 5387528 (1995-02-01), Hutchings et al.
patent: 5891807 (1999-04-01), Muller et al.
patent: A-60-68650 (1985-04-01), None
patent: A-60-158642 (1985-08-01), None
patent: A-6-219759 (1985-11-01), None
patent: A-61-119056 (1986-06-01), None
patent: A-62-136065 (1987-06-01), None
patent: A-62-160731 (1987-07-01), None
patent: A-62-185353 (1987-08-01), None
patent: A-62-293661 (1987-12-01), None
patent: A-63-2371 (1988-01-01), None
patent: A-63-115358 (1988-05-01), None
patent: A-63-166230 (1988-07-01), None
patent: A-63-229845 (1988-09-01), None
patent: A-63-278338 (1988-11-01), None
patent: 64-57623 (1989-03-01), None
patent: A-1-196134 (1989-08-01), None
patent: A-1-216538 (1989-08-01), None
patent: A-2-3956 (1990-01-01), None
patent: 2-260424 (1990-10-01), None
patent: A-2-260660 (1990-10-01), None
patent: A-2-271618 (1990-11-01), None
patent: A-2-271619 (1990-11-01), None
patent: A-2-271620 (1990-11-01), None
patent: A-3-147327 (1991-06-01), None
patent: A-3-252131 (1991-11-01), None
patent: A-4-37152 (1992-02-01), None
patent: 5-102297 (1993-04-01), None
patent: A-5-226298 (1993-09-01), None
patent: B2-5-75184 (1993-10-01), None
patent: B2-6-18248 (1994-03-01), None
patent: B2-6-24228 (1994-03-01), None
patent: B2-7-48547 (1995-05-01), None
patent: B2-2519474 (1996-05-01), None
patent: 8-203863 (1996-08-01), None
patent: B2-2552152 (1996-08-01), None
patent: B2-2589209 (1996-12-01), None
patent: B2-2602808 (1997-01-01), None
patent: B2-2635607 (1997-04-01), None
patent: A-9-162168 (1997-06-01), None
patent: B2-2667552 (1997-06-01), None
patent: B2-2671312 (1997-07-01), None
patent: A-9-283535 (1997-10-01), None
patent: A-9-307101 (1997-11-01), None
patent: 9-330928 (1997-12-01), None
patent: A-9-331063 (1997-12-01), None
patent: B2-2794565 (1998-06-01), None
patent: A-10-229119 (1998-08-01), None
patent: 10-233387 (1998-09-01), None
patent: A-11-97523 (1999-04-01), None
patent: A-11-102961 (1999-04-01), None
patent: 11-135489 (1999-05-01), None
U.S. patent application Ser. No. 09/758,377, Aoki et al., filed Jan. 12, 2001.
S. J. Fonash, “Damage effects in Dry Etching”,Solid State Technology, Apr. 1985, pp. 201-205.
U. S. patent application Ser. No. 08/992,108, Soga, filed Dec. 17, 1997.
U.S. patent application Ser. No. 09/143,513, Ishikawa, filed Aug. 28, 1998.

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