Integrated formation of LDD and non-LDD semiconductor devices

Details Integrated formation of LDD and non-LDD semiconductor devices Integrated formation of LDD and non-LDD semiconductor devices

1998-09-30

2001-10-30

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S231000, C438S291000, C438S303000

Reexamination Certificate

active

06309936

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and methods of making these devices, and more particularly, semiconductor devices with LDD and Non-LDD MOS structures and methods of making these devices.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common and important semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG.
1
. The device generally includes a semiconductor substrate
101
on which a gate electrode
103
is disposed. The gate electrode
103
acts as a conductor. An input signal is typically applied to the gate electrode
103
via a gate terminal (not shown). Heavily-doped source/drain regions
105
are formed in the semiconductor substrate
101
and are connected to source/drain terminals (not shown). As illustrated in
FIG. 1
, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region
107
is formed in the semiconductor substrate
101
beneath the gate electrode
103
and separates the source/drain regions
105
. The channel region
107
is typically lightly doped with a dopant of a type opposite to that of the source/drain regions
105
. In addition, the channel may be doped with a voltage threshold implant to alter the characteristics of the channel region. A punchthrough region may also be formed beneath the channel region
107
to prevent or reduce current leakage. The punchthrough region is typically moderately doped with a dopant of a type opposite to that of the source/drain regions
105
.
The gate electrode
103
is generally separated from the semiconductor substrate
101
by an insulating layer
109
, typically an oxide layer such as SiO
2
. The insulating layer
109
is provided to prevent current from flowing between the gate electrode
103
and the source/drain regions
105
or channel region
107
.
The source/drain regions
105
, illustrated in
FIG. 1
, are lightly-doped-drain (LDD) structures. Each LDD source/drain structure includes a lightly-doped, lower conductivity region
106
near the channel region
107
and a heavily-doped, higher conductivity region
104
adjacent to the lower conductivity region
106
and typically connected to a source/drain terminal. Generally, the LDD source/drain structures are formed by implanting a first dopant into active regions adjacent the gate electrode
103
at relatively low concentration levels to form the lightly-doped regions
106
; forming spacers
102
on sidewalls of the gate electrode
103
; and implanting a second dopant into the active regions at higher concentration levels to form the heavily-doped regions
104
. The substrate is typically annealed to drive the dopant in the heavily-doped regions deeper into the substrate
101
.
Other types of semiconductor devices include source/drain regions without a lightly-doped region adjacent to the channel. These types of source/drain regions, referred to herein as non-LDD source/drain structures, are typically characterized as being relatively heavily doped throughout.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode
103
, a transverse electric field is set up in the channel region
107
. By varying the transverse electric field, it is possible to modulate the conductance of the channel region
107
between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region
107
. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET). Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices.
In many instances, it may be useful to generate a variety of different MOS structures on a single substrate. For example, it may be desirable to form one or more active devices (e.g., transistors) with LDD source/drain structures and one or more active devices (e.g., transistors) with non-LDD source/drain structures on a common substrate. It may also be desirable to form active devices with different gate dielectrics. There is a need for the development of processes for forming semiconductor devices with different MOS structures on a single substrate.
SUMMARY OF THE INVENTION
The present invention provides techniques for forming active devices with LDD source/drain structures and active device with non-LDD source/drain structures and/or devices with different gate dielectrics on a single substrate and in an integrated manner. One embodiment is a method of forming a semiconductor device. A first gate electrode is formed over a substrate and then a spacer is formed on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics formed between the first and second gate electrodes are made of different materials and/or have different thicknesses.
Another embodiment of the invention is another method of forming a semiconductor device. A first dielectric layer is formed over a substrate and a first gate electrode is formed over a region of the first dielectric layer. A spacer is formed on at least one sidewall of the first gate electrode. At least a portion of the first dielectric layer over a substrate region apart from the first gate electrode is removed and then a second dielectric layer is formed over the substrate region after forming the spacer. A second gate electrode is formed over the second dielectric layer.
Yet another embodiment is a semiconductor device formed on a substrate. The device includes a first gate electrode disposed over the substrate and a first dielectric layer disposed between the first gate electrode and the substrate. A first doped source/drain region is formed in the substrate adjacent to the first gate electrode and includes a lightly doped active region adjacent to the first gate electrode and a heavily doped active region adjacent to the lightly doped active region. The device also includes a second gate electrode disposed over the substrate and a second dielectric layer, different from the first dielectric layer, disposed between the second gate electrode and the substrate. A second doped source/drain region is formed in the substrate and includes a heavily doped active region adjacent to the second gate electrode.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The Figures and the detailed description which follow more particularly exemplify these embodiments.


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patent: 5397909 (1995-03-01), Moslehi
patent: 5716861 (1998-02-01), Moslehi
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patent: 5759901

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