Integrated etch process for polysilicon/metal gate

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

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438689, H01L 213205

Patent

active

060603763

ABSTRACT:
A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.

REFERENCES:
patent: 4868617 (1989-09-01), Chiao et al.

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