Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-01-12
2000-05-09
Chaudhari, Chandra
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438689, H01L 213205
Patent
active
060603763
ABSTRACT:
A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.
REFERENCES:
patent: 4868617 (1989-09-01), Chiao et al.
Gabriel Calvin
Harvey Ian Robert
Leard Linda
Lin Xi-Wei
Zheng Tammy
Chaudhari Chandra
Thompson Craig
VLSI Technology Inc.
Weller Douglas L.
LandOfFree
Integrated etch process for polysilicon/metal gate does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated etch process for polysilicon/metal gate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated etch process for polysilicon/metal gate will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1064474