Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2006-10-31
2006-10-31
Deo, Duy-Vu N (Department: 1765)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S623000, C438S725000
Reexamination Certificate
active
07129159
ABSTRACT:
A dual damascene conductor structure is formed on a substrate with an exposed conductor on top covered by a buried cap, a dielectric layer (DL) and an organic layer (OL). Form a lower via hard mask layers over the OL and form a top trench patterning hard mask over the lower, via hard mask. Form a trench pattern hole through the trench hard mask layer; and form a via pattern hole through the via hard mask layer in a region exposed below the trench pattern hole. Etch a via pattern hole into the OL and then etch a via pattern hole down into the DL. Etch away the trench pattern layer and the OL layer below the trench pattern hole. Etch the via hole through the DL exposing the cap while simultaneously partially etching the DL to a final trench depth to form a trench in the DL below the trench pattern hole, with the trench having a bottom above the cap and sidewalls in the DL.
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patent: 6767825 (2004-07-01), Wu
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America William G.
Johnston Steven H.
Deo Duy-Vu N
Jones II Graham S.
Schnurmann H. Daniel
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