Integrated circuits with substrate protrusions, including...

Details Integrated circuits with substrate protrusions, including... Integrated circuits with substrate protrusions, including...

2007-04-24

2008-11-18

Booth, Richard A. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21179

Reexamination Certificate

active

07452776

ABSTRACT:
A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

REFERENCES:
patent: 5654217 (1997-08-01), Yuan et al.
patent: 6262926 (2001-07-01), Nakai
patent: 6714447 (2004-03-01), Satoh et al.
patent: 2007/0018218 (2007-01-01), Kretz et al.
Jeong-Dong Choe et al. “Low Voltage Program/Erase Characteristics of Si Nanocrystal Memory with Damascene Gate FinFET on Bulk Si Wafer,” Journal of Semiconductor Technology and Science, vol. 6, No. 2, Jun. 2006, pp. 68-73.
Laura Peters “Double Gates Prompt Transistor Revolution,” Reed Business Information, a division of Reed Elsevier Inc. Semiconductor International, Mar. 1, 2005, pp. 1-6.

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