Integrated circuits with reduced leakage current

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization

Reexamination Certificate

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Details

C326S034000, C326S112000, C326S119000

Reexamination Certificate

active

11301236

ABSTRACT:
In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

REFERENCES:
patent: 6977519 (2005-12-01), Bhavnagarwala et al.
patent: 7126370 (2006-10-01), Bhattacharya

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