Integrated circuits including metal silicide contacts...

Details Integrated circuits including metal silicide contacts... Integrated circuits including metal silicide contacts...

2000-10-31

2001-11-06

Flynn, Nathan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S344000, C257S368000, C257S369000, C257S382000, C257S383000, C257S384000, C257S388000, C257S408000, C257S412000, C257S413000, C257S900000

Reexamination Certificate

active

06313510

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to methods of fabricating integrated circuits and integrated circuits fabricated thereby, and more particularly to methods of fabricating integrated circuits including metal silicide contacts and integrated circuits fabricated thereby.
BACKGROUND OF THE INVENTION
As the integration density of integrated circuit devices continues to increase, it may become increasingly difficult to form contacts or interconnections between the highly integrated regions of the integrated circuit. Accordingly, many contact technologies have been developed for connecting regions in an integrated circuit.
One type of contact technology is referred to as “butted contact” or “butting contact” technology. Butted contact structures and methods may be used to form an electrical connection between doped regions in an integrated circuit substrate and one or more conductive polysilicon layers on the integrated circuit substrate. Butted contact structures and methods may be employed in Static Random Access Memory (SRAM) cells wherein an electrical connection is formed between a polysilicon gate and a source/drain region in an integrated circuit substrate. Butted contacts are described in U.S. Pat. No. 4,912,540 to Sander et al., U.S. Pat. No. 5,387,535 to Wilmsmeyer and U.S. Pat. No. 5,521,113 to Hsue et al.
FIGS. 1 through 4
illustrate a conventional method for fabricating a butted contact.
FIG. 1
is a cross-sectional view illustrating a step of forming an isolation film
3
(often referred to as a field oxide), first and second gate electrodes
7
a
and
7
b
, and a, Lightly Doped Drain (LDD) region
9
. In detail, the isolation film
3
that defines active and inactive regions is formed in a predetermined area of an integrated circuit substrate such as a silicon semiconductor substrate
1
. Then, a gate oxide layer
5
is formed on the surface of the active region between the isolation films
3
. First and second gate electrodes
7
a
and
7
b
are formed on a predetermined area of the resultant structure having the gate oxide layer
5
.
The first gate electrode
7
a
may correspond to the gate electrode of an access transistor of an SRAM cell, and may form a word line. The second gate electrode
7
b
may correspond to a gate electrode of a driver transistor of the SRAM cell. However, the first and second gate electrodes need not correspond to SRAM cell regions.
The first and second gate electrodes
7
a
and
7
b
may comprise doped polysilicon. Impurity ions are implanted into the surface of the substrate
1
using the first gate electrode
7
a
, the second gate electrode
7
b
and the isolation film
3
as a mask, thereby forming the LDD region
9
on the surface of the active region.
FIG. 2
is a cross-sectional view illustrating a step of forming a sidewall spacer
11
and a source/drain region
14
. First, an oxide or nitride layer is formed on the entire surface of the resultant structure having the LDD region
9
, and anisotropically etched to form the sidewall spacers
11
at the sidewalls of the first and second gate electrodes
7
a
and
7
b
. The surface of the LDD region
9
may be exposed by overetching the oxide or nitride layer to form the sidewall spacers
11
. Then, impurity ions having the same conductivity as that of the LDD region
9
are implanted onto the surface of the silicon substrate
1
using the isolation film
3
, the sidewall spacer
11
and the first and second gate electrodes
7
a
and
7
b
as a mask, thereby forming a heavily doped impurity region
13
having a higher concentration than that of the LDD region
9
. The LDD region
9
and the heavily doped impurity region
13
form the source/drain region
14
of the transistor.
FIG. 3
is a cross-sectional view illustrating a step of forming first, second and third metal silicide layers
16
a
,
16
b
and
16
c
, and a butted contact hole H. A refractory metal layer is formed on the surface of the resultant structure having the source/drain region
14
. A thermal treatment is then performed at a predetermined temperature, thereby simultaneously forming the first and second metal silicide layers
16
a
and
16
b
on the respective first and second gate electrodes
7
a
and
7
b
, and the third metal silicide layer
16
c
on the source/drain region
14
. The refractory metal layer formed on the sidewall spacers
11
and the isolation film
3
does not react to form metal silicide because it is not on a silicon or polysilicon surface. The unreacted refractory metal layer is removed using a chemical solution.
An interlayer dielectric (ILD) film
18
, such as a silicon dioxide layer, is then formed on the resultant structure from which the unreacted refractory metal layer has been removed. The ILD film is then patterned to form a butted contact hole H which exposes the second metal silicide layer
16
b
and the source/drain region
14
adjacent thereto. Unfortunately, if the sidewall spacer
11
is formed of a material having an etching selectivity with respect to the ILD film
18
, the sidewall spacer
11
exposed by the butted contact hole
11
remains as shown in
FIG. 3
, so that the aspect ratio of the butted contact hole
11
may increase. In addition, the sidewall spacer
11
may limit the area of the source/drain region
14
exposed by the butted contact hole H. Finally, a polymer obtained during the etching step of forming the butted contact hole H may be absorbed at the bottom of the butted contact hole H, which may increase the butted contact resistance.
In order to solve these problems, if the sidewall spacer
11
is formed of a material which is the same as the ILD film
18
(such as silicon dioxide), the sidewall spacer
11
formed on the sidewall of the second gate electrode
7
b
may be removed during the overetching step in forming the butted contact hole H. Unfortunately, the LDD region beneath the removed sidewall spacer
11
may be exposed, so that the third metal silicide layer
16
c
may grow to a junction portion of the source/drain region
14
in a subsequent annealing step. Accordingly, the junction leakage current of the source/drain region
14
may increase.
FIG. 4
is a cross-sectional view illustrating the step of forming an interconnection
20
. In detail, a conductive layer is formed on the resultant structure having the butted contact hole H, and then patterned to form an interconnection
20
covering the butted contact hole H. Such a formed interconnection
20
connects the second gate electrode
7
b
and the source/drain region
14
adjacent thereto. Unfortunately, as described above, it may be difficult to increase the area of the source/drain region exposed by the butted contact hole, or to improve the junction leakage current of the source/drain region.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved metal silicide contacts extending between a gate electrode and a source/drain region and methods of fabricating same.
It is another object of the present invention to provide improved contacts extending between a gate electrode and a source/drain region that can increase the area of the source/drain region that is contacted and that can reduce the junction leakage current of the source/drain region, and methods of fabricating the same.
These and other objects are provided according to the present invention, by using the presence and absence of sidewall spacers to provide discontinuous and continuous contacts respectively, between a gate electrode and a source/drain region. In particular, according to the present invention, first and second spaced apart gate electrodes are formed on an integrated circuit substrate. A source/drain region is formed in the integrated circuit substrate therebetween. The first gate electrode includes a first sidewall spacer on a first sidewall thereof facing the second gate electrode. The second gate electrode is free of (i.e. does not include) a sidewall spacer on a second sidewall thereof facing the first electrode. A metal silicide layer is formed on the first gate ele

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