Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2011-04-05
2011-04-05
Nguyen, Viet (Department: 2827)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189170, C365S189080, C365S189120, C365S185030
Reexamination Certificate
active
07920430
ABSTRACT:
In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a plurality of multiple bit information storing memory cells, a plurality of buffer circuits, each buffer circuit being coupled to at least one multiple bit information storing memory cell of the plurality of multiple bit information storing memory cells, and a controller configured to control an access operation to access at least one multiple bit information storing memory cell using the buffer circuit coupled to the at least one multiple bit information storing memory cell to be accessed, and a buffer circuit of at least one other multiple bit information storing memory cell being coupled to at least one other multiple bit information storing memory cell.
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Friederich Christoph
Gutsche Jan
Koebernik Gert
Richter Detlev
Economou John S.
Nguyen Viet
Qimonda AG
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