Integrated circuitry, DRAM cells, capacitors, and methods of...

Details Integrated circuitry, DRAM cells, capacitors, and methods of... Integrated circuitry, DRAM cells, capacitors, and methods of...

1999-03-24

2001-05-15

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S398000

Reexamination Certificate

active

06232176

ABSTRACT:

TECHNICAL FIELD
This invention pertains to integrated circuitry and to methods of forming integrated circuitry. The invention is thought to have particular significance in application to methods of forming dynamic random access memory (DRAM) cell structures, to DRAM cell structures.
BACKGROUND OF THE INVENTION
A commonly used semiconductor memory device is a DRAM cell. A DRAM cell generally consists of a capacitor coupled through a transistor to a bitline. A continuous challenge in the semiconductor industry is to increase DRAM circuit density. Accordingly, there is a continuous effort to decrease the size of memory cell components.
Another continuous trend in the semiconductor industry is to minimize processing steps. Accordingly, it is desirable to utilize common steps for the formation of separate DRAM components. For instance, it is desirable to utilize common steps for the formation of the DRAM capacitor structures and the DRAM bitline contacts.
A semiconductor wafer fragment
10
is illustrated in
FIG. 1
showing a prior art DRAM array
83
. Wafer fragment
10
comprises a semiconductive material
12
, field oxide regions
14
, and wordlines
24
and
26
. Wordlines
24
and
26
comprise a gate oxide layer
16
, a polysilicon layer
18
, a silicide layer
20
and a silicon oxide layer
22
. Silicide layer
20
comprises a refractory metal silicide, such as tungsten silicide, and polysilicon layer
18
typically comprises polysilicon doped with a conductivity enhancing dopant. Nitride spacers
30
are laterally adjacent wordlines
24
and
26
.
Electrical node locations
25
,
27
and
29
are between wordlines
24
and
26
and are electrically connected by transistor gates comprised by wordlines
24
and
26
. Node locations
25
,
27
and
29
are diffusion regions formed within semiconductive material
12
.
A borophosphosilicate glass (BPSG) layer
34
is over semiconductive material
12
and wordlines
24
and
26
. An oxide layer
32
is provided between BPSG layer
34
and material
12
. Oxide layer
32
inhibits diffusion of phosphorus from BPSG layer
34
into underlying materials.
Conductive pedestals
54
,
55
and
56
extend through BPSG layer
34
to node locations
25
,
27
and
29
, respectively. Capacitor constructions
62
and
64
contact upper surfaces of pedestals
54
and
56
, respectively. Capacitor constructions
62
and
64
comprise a storage node layer
66
, a dielectric layer
68
, and a cell plate layer
70
. Dielectric layer
68
comprises an electrically insulative layer, such as silicon nitride. Cell plate layer
70
comprises conductively doped polysilicon, and may alternatively be referred to as a cell layer
70
. Storage node layer
66
comprises conductively doped hemispherical grain polysilicon.
A conductive bitline plug
75
contacts an upper surface of pedestal
55
. Bitline plug
75
may comprise, for example, tungsten. Together, bitline plug
75
and pedestal
55
comprise a bitline contact
77
.
A bitline
76
extends over capacitors
62
and
64
and in electrical connection with bitline contact
77
. Bitline
76
may comprise, for example, aluminum.
The capacitors
62
and
64
are electrically connected to bitline contact
77
through transistor gates comprised by wordlines
26
. A first DRAM cell
79
comprises capacitor
62
electrically connected to bitline
76
through a wordline
26
and bitline contact
77
. A second DRAM cell
81
comprises capacitor
64
electrically connected to bitline
76
through wordline a
26
and bitline contact
77
. DRAM array
83
comprises first and second DRAM cells
79
and
81
.
SUMMARY OF THE INVENTION
The invention includes a number of methods and structures pertaining to integrated circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; methods of forming capacitor and bitline constructions; DRAM memory cell constructions; and capacitor constructions.
The invention encompasses a method of forming an integrated circuit wherein an insulative material layer having an uppermost surface is formed over a first node location and a second node location, and wherein first and second conductive pedestals are formed extending through the insulative material layer and in electrical connection with the first and second node locations, respectively. The conductive pedestals has exposed uppermost surfaces above the uppermost surface of the insulative material layer.
The invention also encompasses an integrated circuit which includes a first node location and a second node location within a semiconductor substrate, the first and second node locations being connectable through a transistor gate and being under an insulative material which has an uppermost surface. The integrated circuit further includes a first conductive pedestal extending through the insulative material layer and in electrical connection with the first node location and a second conductive pedestal extending through the insulative material layer and in electrical connection with the second node location, the conductive pedestals having uppermost surfaces which are substantially at a common elevational height relative to one another and which are above the uppermost surface of the insulative material layer.


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