Integrated circuit with stacked sub-circuits between Vcc and gro

Details Integrated circuit with stacked sub-circuits between Vcc and gro Integrated circuit with stacked sub-circuits between Vcc and gro

1996-01-29

1999-02-02

Tokar, Michael J.

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

326 62, 327530, 307 24, H03K 1900, H01L 2500

Patent

active

058670408

ABSTRACT:
The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.

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Daisaburo Takashima, et al. "Low-Power On-Chip Supply Voltage Conversion Scheme for Ultrahigh-Density DRAM'S", IEEE Journal of Solid-State Circuits, vol. 28, No. 4, Apr. 1993, pp. 504-509.

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