Integrated circuit with improved channel stress properties...

Details Integrated circuit with improved channel stress properties... Integrated circuit with improved channel stress properties...

2006-05-16

2006-05-16

Luu, Chuong Anh (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S763000, C438S744000, C438S158000

Reexamination Certificate

active

07045408

ABSTRACT:
An integrated circuit is described that comprises a PMOS transistor and an NMOS transistor that are formed on a semiconductor substrate. A silicate glass layer is formed on only the PMOS transistor or the NMOS transistor; and an etch stop layer is formed on the silicate glass layer. Also described is a method for forming an integrated circuit. That method comprises forming a PMOS transistor structure and an NMOS transistor structure on a semiconductor substrate, forming a silicate glass layer on only the PMOS transistor structure or the NMOS transistor structure, and forming an etch stop layer on the silicate glass layer.

REFERENCES:
patent: 5633202 (1997-05-01), Brigham et al.
patent: 6228777 (2001-05-01), Arafa et al.
patent: 6372569 (2002-04-01), Lee et al.
patent: 6638807 (2003-10-01), Forbes et al.
patent: 6762085 (2004-07-01), Zheng et al.
patent: 2002/0113295 (2002-08-01), Nakamura

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