Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-06-07
2005-06-07
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000, C438S288000, C438S335000
Reexamination Certificate
active
06902967
ABSTRACT:
An integrated circuit having a MOS structure with reduced parasitic bipolar transistor action. In one embodiment, a MOS integrated circuit device comprises a substrate having a working surface, at least one body region and for each body region a source and a layer of narrow band gap material. Each body region is formed in the substrate proximate the working surface of the substrate. Each layer of narrow band gap material is positioned in a portion of its associated body region and proximate the working surface of the substrate. Each layer of narrow band gap material has a band gap that is narrower than the band gap of the substrate in which each of the body regions are formed. Each source region is formed in an associated body region. At least a portion of each source region is also formed in an associated layer of narrow band gap material.
REFERENCES:
patent: 4564770 (1986-01-01), Sherman et al.
patent: 4969852 (1990-11-01), Osterwald
patent: 5138177 (1992-08-01), Morgan et al.
patent: 5698867 (1997-12-01), Bauer et al.
patent: 5821144 (1998-10-01), D'Anna et al.
patent: 6035235 (2000-03-01), Perttu et al.
patent: 6133107 (2000-10-01), Menegoli
patent: 6166925 (2000-12-01), Richter et al.
patent: 6172398 (2001-01-01), Hshieh
patent: 6239958 (2001-05-01), Kato et al.
patent: 6306691 (2001-10-01), Koh
patent: 6368920 (2002-04-01), Beasom
patent: 6406962 (2002-06-01), Agnello et al.
patent: 2001/0048119 (2001-12-01), Mizuno et al.
patent: 2002/0017684 (2002-02-01), Blanchard et al.
patent: 0747966 (1996-11-01), None
patent: 0747958 (1996-12-01), None
patent: 63281468 (1998-11-01), None
patent: 7-193231 (2001-09-01), None
patent: WO 00/10204 (2000-02-01), None
Muller et al., Device Electronics For Integrated Circuits, Wiley, Second Edition, 54-56.
Fogg and Associates LLC
Intersil America's Inc.
Lundberg Scott V.
LandOfFree
Integrated circuit with a MOS structure having reduced... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit with a MOS structure having reduced..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with a MOS structure having reduced... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3520310