Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2011-03-29
2011-03-29
Nguyen, Dao H (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S174000, C438S186000, C438S188000, C438S196000, C257S256000, C257S268000, C257S270000, C257S272000, C257S403000, C257SE21445, C257SE21446, C257SE29059, C257SE29312
Reexamination Certificate
active
07915107
ABSTRACT:
This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
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Baker & Botts L.L.P.
Nguyen Dao H
SuVolta, Inc.
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