Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-05-03
2005-05-03
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S622000, C438S637000, C438S639000
Reexamination Certificate
active
06887779
ABSTRACT:
A semiconductor chip carrier having an increased chip connector and plated through hole density. In particular, a substrate having a plurality of plated through holes therein, and a fatigue resistant redistribution layer thereon. The redistribution layer includes a plurality of vias selectively positioned over and contacting the plated through holes. The substrate further including a ground plane, two pair of signal planes, and two pair of power planes, wherein the second pair of power planes are located directly underneath the external dielectric layer. A buried plated through hole within the substrate.
REFERENCES:
patent: 4710854 (1987-12-01), Yamada et al.
patent: 5072075 (1991-12-01), Lee et al.
patent: 5121190 (1992-06-01), Hsiao et al.
patent: 5487218 (1996-01-01), Bhatt et al.
patent: 5557844 (1996-09-01), Bhatt et al.
patent: 5574630 (1996-11-01), Kresge et al.
patent: 5615087 (1997-03-01), Wieloch
patent: 5792705 (1998-08-01), Wang et al.
patent: 5798563 (1998-08-01), Feilchenfeld et al.
patent: 5876842 (1999-03-01), Duffy et al.
patent: 5894173 (1999-04-01), Jacobs et al.
patent: 5900675 (1999-05-01), Appelt et al.
patent: 5906042 (1999-05-01), Lan et al.
patent: 5929729 (1999-07-01), Swarup
patent: 6000130 (1999-12-01), Chang et al.
patent: 6388208 (2002-05-01), Kiani et al.
“High Performance Carrier Technology: Materials And Fabrication”, by Light et al, 1993 International Electronics Packaging Conference, San Diego, California, vol. One.
“High Performance Carrier Technology”, by Heck et al, 1993 International Electronics Packaging Conference, San Diego, California, vol. One.
“Process Considerations in the Fabrication of Teflon Printed Circuit Boards”, by Light et al, 1994 Proceedings, 44 Electronic Components & Technology Conference, May 1994.
Alcoe David J.
Downes, Jr. Francis J.
Jones Gerald W.
Kresge John S.
Tytran-Palomaki Cheryl L.
Hogans David L.
Jr. Carl Whitehead
Schmeiser Olsen & Watts
Steinberg William H.
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