Integrated circuit power management for reducing leakage...

Details Integrated circuit power management for reducing leakage... Integrated circuit power management for reducing leakage...

2005-07-12

2005-07-12

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Powering

C365S227000

Reexamination Certificate

active

06917555

ABSTRACT:
Leakage current is eliminated in a memory array during a low power mode of a processing system having a processor that interfaces with the memory array. Because two power planes are created, the processor may continue executing instructions using a system memory while bypassing the memory array when the array is powered down. A switch selectively removes electrical connectivity to a supply voltage terminal in response to either processor-initiated control resulting from execution of an instruction or from a source originating in the system somewhere else than the processor. Upon restoration of power to the memory array, data may or may not need to be marked as unusable depending upon which of the two power planes supporting arrays to the memory array are located. Predetermined criteria may be used to control the timing of the restoration of power. Multiple arrays may be implemented to independently reduce leakage current.

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