Integrated circuit polishing method

Details Integrated circuit polishing method Integrated circuit polishing method

1992-03-27

1994-05-24

Thomas, Tom

Fishing, trapping, and vermin destroying

437974, 156636, H01L 21302

Patent

active

053148436

ABSTRACT:
A semiconductor wafer has a surface layer to be planarized in a chemical mechanical polishing (CMP) process. An area of the layer that is higher than another area is altered so that the removal rate is higher. For example, if the surface layer is TEOS oxide, the higher layer may be bombarded with boron and phosphorus to produce BPSG, which has a polishing rate 2-3 times that of the TEOS. Upon CMP planarization, the higher area erodes faster resulting in improved planarization. Alternatively, the lower area may be doped with nitrogen to produce a nitride which is more resistant to CMP, with the same result. Likewise areas, such as tungsten troughs, which tend to be dished by CMP, may be changed to WNx which is more resistant to the tungsten CMP than the adjacent tungsten, eliminating the dishing upon planarization.

REFERENCES:
patent: 4735679 (1988-04-01), Lasky
patent: 4839311 (1989-06-01), Riley et al.
patent: 4847111 (1989-07-01), Chow et al.
patent: 4956313 (1990-09-01), Cote et al.
patent: 4992135 (1991-02-01), Doan
patent: 5064777 (1991-11-01), Dhong et al.
patent: 5169491 (1992-12-01), Doan
R. S. Bennett et al., "Selective Planarization Process and Structures," IBM Tech. Disc. Bull., vol. 27, No. 4B, Sep. 1984, pp. 2560-2563.
G. H. Schwuttke et al., "New Gettering Process Using Laser-Induced Damage . . . ," IBM Technical Disclosure Bulletin, vol. 26, No. 1, Jun. 1983, p. 245.
W. L. C. M. Heyboer et al., "Chemomechanical Silicon Polishing", J. Electrochem. Society, vol. 138, No. 3, Mar. 1991, pp. 774-777.
"Enhanced Metal Polish: Corrosion Control by Temperature Friction . . . " International Technology Disclosures, vol. 9, No. 8, Aug. 25, 1991.
G. S. Oehrlein et al., "Competitive Reactions of Fluorine and Oxygen with W, WSi, and Si Surfaces . . . " J. Vac. Sci. Tech A, vol. 7, No. 3, May/Jun. 1989, pp. 1035-1041.

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