Integrated circuit packaging system with stacked die and...

Details Integrated circuit packaging system with stacked die and... Integrated circuit packaging system with stacked die and...

2011-07-12

2011-07-12

Luu, Chuong A. (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S686000, C257S777000, C257S784000, C438S106000, C438S108000, C438S109000

Reexamination Certificate

active

07977802

ABSTRACT:
A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die.

REFERENCES:
patent: 6777797 (2004-08-01), Egawa
patent: 7242101 (2007-07-01), Ararao et al.
patent: 7432604 (2008-10-01), Farnworth et al.
patent: 7456108 (2008-11-01), Fukazawa
patent: 7459776 (2008-12-01), St. Amand et al.
patent: 2003/0162325 (2003-08-01), Tan et al.
patent: 2007/0052082 (2007-03-01), Lee et al.

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