Integrated circuit packages with reduced stress on die and...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S778000, C257S779000

Reexamination Certificate

active

06989586

ABSTRACT:
Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

REFERENCES:
patent: 6201707 (2001-03-01), Sota
patent: 6571245 (2003-05-01), Huang et al.
patent: 2003/0034565 (2003-02-01), Lan et al.
patent: 2003/0157747 (2003-08-01), Chen et al.
Harper, Electronic Packaging Interconnection Handbook, 1991, McGraw-Hill, 5.1-5.5.
Wolf et al., Silicon Processing for the VLSI Era, 2000, vol. I, Lattice Press, 719-727, 791-795.

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